MT48LC128M4A2TG MICRON [Micron Technology], MT48LC128M4A2TG Datasheet - Page 35

• Manufacturer Part Number: MT48LC128M4A2TG
• Description: SYNCHRONOUS DRAM
• Manufacturer: MICRON [Micron Technology]

NOTES
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11. AC timing and I
12. Other input signals are allowed to transition no
512Mb: x4, x8, x16 SDRAM
512MSDRAM_D.p65 – Rev. D; Pub 1/02
All voltages referenced to V
This parameter is sampled. V
f = 1 MHz, T
I
rates. Specified values are obtained with minimum
cycle time and the outputs open.
Enables on-chip refresh and address counters.
The minimum specifications are used only to
indicate cycle time at which proper operation over
the full temperature range (0°C ≤ T
ensured.
An initial pause of 100µs is required after power-
up, followed by two AUTO REFRESH commands,
before proper device operation is ensured. (V
and V
and V
AUTO REFRESH command wake-ups should be
repeated any time the
exceeded.
AC characteristics assume
In addition to meeting the transition rate specifi-
cation, the clock and CKE must transit between V
and V
manner.
Outputs measured at 1.5V with equivalent load:
t
the open circuit condition; it is not a reference to
V
t
with timing referenced to 1.5V crossover point. If
the input transition time is longer than 1 ns, then
the timing is referenced at V
and no longer at the 1.5V crossover point.
more than once every two clocks and are otherwise
at valid V
HZ defines the time at which the output achieves
OH before going High-Z.
DD
OH
is dependent on output loading and cycle
or V
DD
SS
IL
Q must be at same potential.) The two
(or between V
Q must be powered up simultaneously. V
OL
IH
. The last valid data element will meet
or V
A
= 25°C; pin under test biased at 1.4V.
Q
IL
DD
levels.
tests have V
IL
t
REF refresh requirement is
and V
t
SS
T = 1ns.
IL
.
DD
IH
(MAX) and V
IL
) in a monotonic
, V
= 0V and V
50pF
DD
A
Q = +3.3V;
≤ 70°C) is
IH
IH
DD
(MIN)
= 3V,
SS
IH
35
13. I
14. Timing actually specified by
15. Timing actually specified by
16. Timing actually specified by
17. Required clocks are specified by JEDEC functional-
18. The I
19. Address transitions average one transition every
20. CLK must be toggled a minimum of two times
21. Based on
22. V
23. The clock frequency must remain constant (stable
24. Auto precharge mode only. The precharge timing
25. Precharge mode only.
26. JEDEC and PC100, PC133 specify three clocks.
27.
28. Parameter guaranteed by design.
29. For -75, CL = 3,
30. CKE is HIGH during refresh command period
properly initialized.
specified as a reference only at minimum cycle
rate.
specified as a reference only at minimum cycle
rate.
ity and are not dependent on any timing param-
eter.
proportional amount by the amount the frequency
is altered for the test condition.
two clocks.
during this period.
width ≤ 3ns, and the pulse width cannot be greater
than one third of the cycle rate. V
(MIN) = -2V for a pulse width ≤ 3ns.
clock is defined as a signal cycling within timing
constraints specified for the clock pin) during
access or precharge states (READ, WRITE, includ-
ing
be used to reduce the data rate.
budget (
delay, after the last WRITE is executed.
t
guaranteed by design.
t
t
actually a nominal value and does not result in a
fail value.
AC for -75/-7E at CL = 3 with no load is 4.6ns and is
CK = 7.5ns
RFC(MIN) else CKE is LOW. The I
DD
IH
Micron Technology, Inc., reserves the right to change products or specifications without notice.
overshoot: V
specifications are tested after the device is
t
WR, and PRECHARGE commands). CKE may
DD
current will increase or decrease in a
t
RP) begins 7.5ns/7ns after the first clock
t
CK = 7.5ns for -75 and -7E.
IH
t
CK = 7.5ns; For -7E, CL = 2,
(MAX) = V
512Mb: x4, x8, x16
DD
t
t
t
CKS; clock(s)
WR plus
WR.
Q + 2V for a pulse
IL
DD
©2000, Micron Technology, Inc.
undershoot: V
6 limit is
SDRAM
ADVANCE
t
RP; clock(s)
IL