MT48LC128M4A2TG MICRON [Micron Technology], MT48LC128M4A2TG Datasheet - Page 47

• Manufacturer Part Number: MT48LC128M4A2TG
• Description: SYNCHRONOUS DRAM
• Manufacturer: MICRON [Micron Technology]

TIMING PARAMETERS
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 4, and the CAS latency = 2.
512Mb: x4, x8, x16 SDRAM
512MSDRAM_D.p65 – Rev. D; Pub 1/02
A0-A9, A11, A12
DQML, DQMH
SYMBOL*
t
t
t
t
t
t
t
t
t
AC (3)
AC (2)
AH
AS
CH
CL
CK (3)
CK (2)
CKH
COMMAND
BA0, BA1
DQM/
2. x16: A11 and A12 = “Don’t Care”
CLK
CKE
A10
DQ
x8: A12 = “Don’t Care”
t CKS
t CMS t CMH
t AS
t AS
t AS
ACTIVE
T0
ROW
ROW
BANK
t CKH
t AH
t AH
t AH
t RCD
MIN
0.8
1.5
2.5
2.5
7.5
0.8
7
t CK
-7E
T1
NOP
MAX
5.4
5.4
DISABLE AUTO PRECHARGE
ENABLE AUTO PRECHARGE
t CMS
t CL
MIN
COLUMN m 2
0.8
1.5
2.5
2.5
7.5
0.8
10
T2
READ
BANK
-75
t CMH
READ – DQM OPERATION
t CH
MAX
CAS Latency
5.4
6
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
T3
NOP
t
LZ
t AC
47
T4
NOP
t OH
D
SYMBOL*
t
t
t
t
t
t
t
t
CKS
CMH
CMS
HZ (3)
HZ (2)
LZ
OH
RCD
t HZ
OUT
m
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T5
NOP
t
LZ
t AC
1
T6
NOP
512Mb: x4, x8, x16
MIN
D
1.5
0.8
1.5
2.7
15
1
t OH
t AC
OUT
m + 2
-7E
MAX
5.4
5.4
T7
NOP
D
OUT
t OH
MIN
t HZ
1.5
0.8
1.5
2.7
20
1
m + 3
©2000, Micron Technology, Inc.
-75
SDRAM
ADVANCE
MAX
5.4
6
T8
NOP
DON’T CARE
UNDEFINED
UNITS
ns
ns
ns
ns
ns
ns
ns
ns