MT48LC128M4A2TG MICRON [Micron Technology], MT48LC128M4A2TG Datasheet - Page 46

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MT48LC128M4A2TG

Manufacturer Part Number
MT48LC128M4A2TG
Description
SYNCHRONOUS DRAM
Manufacturer
MICRON [Micron Technology]
Datasheet
A0-A9, A11, A12
TIMING PARAMETERS
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the CAS latency = 2.
512Mb: x4, x8, x16 SDRAM
512MSDRAM_D.p65 – Rev. D; Pub 1/02
DQML, DQMH
SYMBOL*
t
t
t
t
t
t
t
t
t
AC (3)
AC (2)
AH
AS
CH
CL
CK (3)
CK (2)
CKH
COMMAND
BA0, BA1
DQM/
CKE
A10
CLK
2. x16: A11 and A12 = “Don’t Care”
3. Page left open; no
DQ
x8: A12 = “Don’t Care”
t CKS
t CMS
t AS
t AS
t AS
ACTIVE
BANK
T0
ROW
ROW
t CKH
t CMH
t AH
t AH
t AH
t RCD
t CL
MIN
0.8
1.5
2.5
2.5
7.5
0.8
7
T1
NOP
t CH
-7E
t
RP.
MAX
5.4
5.4
t CMS
t CK
COLUMN m 2
T2
BANK
READ
t CMH
MIN
0.8
1.5
2.5
2.5
7.5
0.8
10
CAS Latency
-75
READ – FULL-PAGE BURST
MAX
5.4
6
T3
NOP
t LZ
UNITS
t AC
ns
ns
ns
ns
ns
ns
ns
ns
ns
T4
D
NOP
OUT
t OH
46
m
1,024 (x16) locations within same row
2,048 (x8) locations within same row
4,096 (x4) locations within same row
t AC
Full-page burst does not self-terminate.
Can use BURST TERMINATE command.
SYMBOL*
t
t
t
t
t
t
t
t
CKS
CMH
CMS
HZ (3)
HZ (2)
LZ
OH
RCD
D
T5
OUT
NOP
t OH
m+1
Full page completed
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t AC
D
T6
OUT
NOP
1
t OH
t AC
m+2
(
(
(
(
(
(
)
(
)
(
)
(
)
(
(
)
)
)
)
)
)
)
(
(
(
(
)
(
)
(
)
(
(
(
(
(
(
)
(
)
(
)
(
)
(
(
)
)
)
)
(
(
(
)
)
)
)
)
)
(
)
(
)
(
)
)
)
)
Tn + 1
D
512Mb: x4, x8, x16
NOP
MIN
OUT
1.5
0.8
1.5
2.7
15
1
t OH
m-1
-7E
t AC
MAX
5.4
5.4
BURST TERM
Tn + 2
3
Dout m
t OH
MIN
1.5
0.8
1.5
2.7
20
t AC
1
©2000, Micron Technology, Inc.
-75
SDRAM
ADVANCE
Tn + 3
MAX
D
5.4
OUT
NOP
6
DON’T CARE
UNDEFINED
t OH
m+1
t HZ
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
Tn + 4
NOP

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