MT48LC128M4A2TG MICRON [Micron Technology], MT48LC128M4A2TG Datasheet - Page 25

• Manufacturer Part Number: MT48LC128M4A2TG
• Description: SYNCHRONOUS DRAM
• Manufacturer: MICRON [Micron Technology]

CONCURRENT AUTO PRECHARGE
bank while an access command with auto precharge
enabled is executing is not allowed by SDRAMs, unless
the SDRAM supports CONCURRENT AUTO PRECHARGE.
Micron SDRAMs support CONCURRENT AUTO
PRECHARGE. Four cases where CONCURRENT AUTO
PRECHARGE occurs are defined below.
READ with auto precharge
1. Interrupted by a READ (with or without auto
512Mb: x4, x8, x16 SDRAM
512MSDRAM_D.p65 – Rev. D; Pub 1/02
An access command to (READ or WRITE) another
precharge): A READ to bank m will interrupt a READ
Internal
States
NOTE: DQM is LOW.
READ With Auto Precharge Interrupted by a WRITE
READ With Auto Precharge Interrupted by a READ
Internal
States
NOTE: 1. DQM is HIGH at T2 to prevent D
COMMAND
ADDRESS
BANK m
BANK n
COMMAND
CLK
ADDRESS
DQ
BANK m
BANK n
DQM
CLK
DQ
1
Page Active
T0
NOP
Active
Page
READ - AP
BANK n,
BANK n
COL a
T0
READ with Burst of 4
CAS Latency = 3 (BANK n)
READ - AP
BANK n,
Page Active
BANK n
COL a
T1
Page Active
READ with Burst of 4
CAS Latency = 3 (BANK n)
T1
NOP
OUT
-a+1 from contending with D
Figure 25
Figure 24
T2
NOP
T2
NOP
25
BANK m,
READ - AP
T3
BANK m
COL d
T3
D
NOP
OUT
a
2. Interrupted by a WRITE (with or without auto
Interrupt Burst, Precharge
CAS Latency = 3 (BANK m)
READ with Burst of 4
on bank n, CAS latency later. The PRECHARGE to
bank n will begin when the READ to bank m is regis-
tered (Figure 24).
precharge): A WRITE to bank m will interrupt a READ
on bank n when registered. DQM should be used two
clocks prior to the WRITE command to prevent bus
contention. The PRECHARGE to bank n will begin
when the WRITE to bank m is registered (Figure 25).
BANK m,
WRITE - AP
COL d
BANK m
T4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D
T4
d
IN
IN
Interrupt Burst, Precharge
NOP
WRITE with Burst of 4
-d at T4.
D
OUT
a
t
RP - BANK n
T5
d + 1
NOP
D
IN
T5
NOP
t
RP - BANK n
D
a + 1
OUT
T6
d + 2
NOP
D
IN
T6
512Mb: x4, x8, x16
NOP
DON’T CARE
D
OUT
d
T7
t WR - BANK m
d + 3
NOP
D
IN
Write-Back
Idle
Idle
T7
NOP
t RP - BANK m
Precharge
D
d + 1
OUT
©2000, Micron Technology, Inc.
SDRAM
ADVANCE