MT48LC128M4A2TG MICRON [Micron Technology], MT48LC128M4A2TG Datasheet - Page 31

• Manufacturer Part Number: MT48LC128M4A2TG
• Description: SYNCHRONOUS DRAM
• Manufacturer: MICRON [Micron Technology]

NOTE (continued):
512Mb: x4, x8, x16 SDRAM
512MSDRAM_D.p65 – Rev. D; Pub 1/02
10. For a READ without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m
11. For a READ without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m
12. For a WRITE without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m
13. For a WRITE without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m
14. For a READ with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will
15. For a READ with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will
16. For a WRITE with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will
17. For a WRITE with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will
4. AUTO REFRESH, SELF REFRESH and LOAD MODE REGISTER commands may only be issued when all banks are idle.
5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current
6. All states and sequences not shown are illegal or reserved.
7. READs or WRITEs to bank m listed in the Command (Action) column include READs or WRITEs with auto precharge
8. CONCURRENT AUTO PRECHARGE: Bank n will initiate the auto precharge command when its burst has been
9. Burst in bank n continues as initiated.
state only.
enabled and READs or WRITEs with auto precharge disabled.
interrupted by bank m’s burst.
will interrupt the READ on bank n, CAS latency later (Figure 7).
will interrupt the READ on bank n when registered (Figures 9 and 10). DQM should be used one clock prior to the
WRITE command to prevent bus contention.
will interrupt the WRITE on bank n when registered (Figure 17), with the data-out appearing CAS latency later. The
last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m.
will interrupt the WRITE on bank n when registered (Figure 15). The last valid WRITE to bank n will be data-in
registered one clock prior to the READ to bank m.
interrupt the READ on bank n, CAS latency later. The PRECHARGE to bank n will begin when the READ to bank m is
registered (Figure 24).
interrupt the READ on bank n when registered. DQM should be used two clocks prior to the WRITE command to
prevent bus contention. The PRECHARGE to bank n will begin when the WRITE to bank m is registered (Figure 25).
interrupt the WRITE on bank n when registered, with the data-out appearing CAS latency later. The PRECHARGE to
bank n will begin after
bank n will be data-in registered one clock prior to the READ to bank m (Figure 26).
interrupt the WRITE on bank n when registered. The PRECHARGE to bank n will begin after
begins when the WRITE to bank m is registered. The last valid WRITE to bank n will be data registered one clock prior
to the WRITE to bank m (Figure 27).
t
WR is met, where
t
WR begins when the READ to bank m is registered. The last valid WRITE to
31
Micron Technology, Inc., reserves the right to change products or specifications without notice.
512Mb: x4, x8, x16
t
WR is met, where
©2000, Micron Technology, Inc.
SDRAM
ADVANCE
t
WR