MT48LC128M4A2TG MICRON [Micron Technology], MT48LC128M4A2TG Datasheet - Page 51

• Manufacturer Part Number: MT48LC128M4A2TG
• Description: SYNCHRONOUS DRAM
• Manufacturer: MICRON [Micron Technology]

A0-A9, A11, A12
TIMING PARAMETERS
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 1, and the WRITE burst is followed by a “manual” PRECHARGE.
512Mb: x4, x8, x16 SDRAM
512MSDRAM_D.p65 – Rev. D; Pub 1/02
DQML, DQMH
SYMBOL*
t
t
t
t
t
t
t
t
t
AH
AS
CH
CL
CK (3)
CK (2)
CKH
CKS
CMH
COMMAND
BA0, BA1
DQM/
CLK
CKE
A10
2. 14ns to 15ns is required between <D
3. x16: A11 and A12 = “Don’t Care”
4. WRITE command not allowed else
DQ
x8: A12 = “Don’t Care”
t CMS
t CKS
t AS
t AS
t AS
ACTIVE
T0
ROW
ROW
BANK
t CMH
t CKH
t AH
t AH
t AH
t RCD 3
t RAS
t RC
t CK
MIN
0.8
1.5
2.5
2.5
7.5
0.8
1.5
0.8
7
T1
NOP 4
-7E
MAX
SINGLE WRITE – WITH AUTO PRECHARGE
t CL
NOP 4
T2
MIN
0.8
1.5
2.5
2.5
7.5
0.8
1.5
0.8
10
t CH
-75
t
RAS would be violated
MAX
IN
m> and the PRECHARGE command, regardless of frequency.
NOP 4
T3
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ENABLE AUTO PRECHARGE
t CMS
t DS
COLUMN m
BANK
WRITE
T4
D
IN
t CMH
51
t DH
m
3
t WR
2
SYMBOL*
t
t
t
t
t
t
t
t
CMS
DH
DS
RAS
RC
RCD
RP
WR
T5
NOP
Micron Technology, Inc., reserves the right to change products or specifications without notice.
NOP
T6
t RP
1 CLK +
512Mb: x4, x8, x16
MIN
7ns
1.5
0.8
1.5
37
60
15
15
T7
1
NOP
-7E
120,000
MAX
ACTIVE
ROW
BANK
ROW
T8
1 CLK +
MIN
7ns
1.5
0.8
1.5
44
66
20
20
©2000, Micron Technology, Inc.
-75
120,000
DON’T CARE
SDRAM
ADVANCE
MAX
T9
NOP
UNITS
ns
ns
ns
ns
ns
ns
ns
ns