MT48LC128M4A2TG MICRON [Micron Technology], MT48LC128M4A2TG Datasheet - Page 16

• Manufacturer Part Number: MT48LC128M4A2TG
• Description: SYNCHRONOUS DRAM
• Manufacturer: MICRON [Micron Technology]

latencies of two and three; data element n + 3 is either the
last of a burst of four or the last desired of a longer burst.
The 512Mb SDRAM uses a pipelined architecture and
therefore does not require the 2n rule associated with a
prefetch architecture. A READ command can be initiated
512Mb: x4, x8, x16 SDRAM
512MSDRAM_D.p65 – Rev. D; Pub 1/02
COMMAND
COMMAND
ADDRESS
ADDRESS
NOTE: Each READ command may be to any bank. DQM is LOW.
CLK
CLK
DQ
DQ
BANK,
T0
T0
COL n
BANK,
COL n
READ
READ
CAS Latency = 2
CAS Latency = 3
T1
T1
NOP
NOP
Consecutive READ Bursts
T2
T2
NOP
NOP
D
OUT
n
Figure 7
T3
T3
16
NOP
NOP
D
n + 1
D
OUT
OUT
n
on any clock cycle following a previous READ command.
Full-speed random read accesses can be performed to
the same bank, as shown in Figure 8, or each subsequent
READ may be performed to a different bank.
T4
T4
BANK,
BANK,
READ
COL b
READ
COL b
Micron Technology, Inc., reserves the right to change products or specifications without notice.
X = 1 cycle
n + 2
D
n + 1
D
OUT
OUT
X = 2 cycles
T5
T5
NOP
NOP
n + 2
n + 3
D
D
OUT
OUT
512Mb: x4, x8, x16
T6
T6
NOP
NOP
n + 3
D
D
OUT
OUT
b
DON’T CARE
T7
NOP
©2000, Micron Technology, Inc.
D
OUT
SDRAM
ADVANCE
b