MT48LC128M4A2TG MICRON [Micron Technology], MT48LC128M4A2TG Datasheet - Page 41

• Manufacturer Part Number: MT48LC128M4A2TG
• Description: SYNCHRONOUS DRAM
• Manufacturer: MICRON [Micron Technology]

TIMING PARAMETERS
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 4, the CAS latency = 2, and the READ burst is followed by a “manual”
512Mb: x4, x8, x16 SDRAM
512MSDRAM_D.p65 – Rev. D; Pub 1/02
A0-A9, A11, A12
DQML, DQMH
SYMBOL*
t
t
t
t
t
t
t
t
t
t
AC (3)
AC (2)
AH
AS
CH
CL
CK (3)
CK (2)
CKH
CKS
COMMAND
BA0, BA1
DQM/
2. x16: A11 and A12 = “Don’t Care”
CKE
A10
CLK
DQ
PRECHARGE.
x8: A12 = “Don’t Care”
t CMS
t CKS
t AS
t AS
t AS
ACTIVE
T0
ROW
ROW
BANK
t CKH
t CMH
t AH
t AH
t AH
t RCD
t RAS
t RC
MIN
0.8
1.5
2.5
2.5
7.5
0.8
1.5
t CK
7
-7E
T1
NOP
MAX
5.4
5.4
DISABLE AUTO PRECHARGE
READ – WITHOUT AUTO PRECHARGE
t CMS
t CL
MIN
COLUMN m 2
0.8
1.5
2.5
2.5
7.5
0.8
1.5
10
T2
BANK
READ
-75
t CMH
t CH
MAX
CAS Latency
5.4
6
UNITS
T3
NOP
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t LZ
t AC
41
T4
NOP
D
OUT
t OH
t AC
m
SYMBOL*
t
t
t
t
t
t
t
t
t
t
CMH
CMS
HZ (3)
HZ (2)
LZ
OH
RAS
RC
RCD
RP
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D
T5
OUT
NOP
m + 1
t OH
t AC
SINGLE BANK
PRECHARGE
ALL BANKS
D
BANK
T6
OUT
1
512Mb: x4, x8, x16
MIN
t OH
m + 2
0.8
1.5
2.7
37
60
15
15
1
t RP
t AC
-7E
120,000
MAX
5.4
5.4
D
T7
NOP
OUT
m + 3
t OH
t HZ
MIN
0.8
1.5
2.7
44
66
20
20
1
©2000, Micron Technology, Inc.
-75
120,000
SDRAM
ADVANCE
MAX
5.4
BANK
T8
ROW
ROW
ACTIVE
6
DON’T CARE
UNDEFINED
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns