MT48LC128M4A2TG MICRON [Micron Technology], MT48LC128M4A2TG Datasheet - Page 43

• Manufacturer Part Number: MT48LC128M4A2TG
• Description: SYNCHRONOUS DRAM
• Manufacturer: MICRON [Micron Technology]

512Mb: x4, x8, x16 SDRAM
512MSDRAM_D.p65 – Rev. D; Pub 1/02
A0-A9, A11, A12
TIMING PARAMETERS
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 1, the CAS latency = 2, and the READ burst is followed by a “manual”
DQML, DQMH
SYMBOL*
t
t
t
t
t
t
t
t
t
t
AC (3)
AC (2)
AH
AS
CH
CL
CK (3)
CK (2)
CKH
CKS
COMMAND
BA0, BA1
DQM/
2. x16: A11 and A12 = “Don’t Care”
CKE
CLK
A10
DQ
PRECHARGE.
x8: A12 = “Don’t Care”
t CMS
t CKS
t AS
t AS
t AS
ACTIVE
ROW
ROW
BANK
T0
t CMH
t CKH
t AH
t AH
t AH
t RCD
t RAS
t RC
MIN
0.8
1.5
2.5
2.5
7.5
0.8
1.5
t CK
7
-7E
T1
NOP
SINGLE READ – WITHOUT AUTO PRECHARGE
MAX
5.4
5.4
DISABLE AUTO PRECHARGE
t CMS
t CL
COLUMN m
MIN
0.8
1.5
2.5
2.5
7.5
0.8
1.5
10
BANK
T2
READ
t CMH
-75
t CH
CAS Latency
MAX
2
5.4
6
UNITS
T3
NOP
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t LZ
t AC
43
T4
D
NOP
OUT
t OH
t HZ
m
SYMBOL*
t
t
t
t
t
t
t
t
t
t
CMH
CMS
HZ (3)
HZ (2)
LZ
OH
RAS
RC
RCD
RP
Micron Technology, Inc., reserves the right to change products or specifications without notice.
SINGLE BANKS
PRECHARGE
ALL BANKS
BANK(S)
T5
t RP
T6
NOP
512Mb: x4, x8, x16
MIN
0.8
1.5
2.7
37
60
15
15
1
-7E
1
120,000
MAX
5.4
5.4
ACTIVE
BANK
ROW
T7
ROW
MIN
0.8
1.5
2.7
44
66
20
20
1
©2000, Micron Technology, Inc.
-75
120,000
SDRAM
ADVANCE
T8
MAX
NOP
5.4
6
DON’T CARE
UNDEFINED
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns