cx29503 Mindspeed Technologies, cx29503 Datasheet - Page 71
cx29503
Manufacturer Part Number
cx29503
Description
Cx29503 Broadband Access Multiplexer Data Sheet
Manufacturer
Mindspeed Technologies
Datasheet
1.CX29503.pdf
(388 pages)
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CX29503 Data Sheet
2.8
Figure 2-10. DS1/E1 Framer Core Block Diagram
29503-DSH-002-B
RCLKI
RPOS
TPOS
Local
Frame
Loopback
Path
Loopback
Path
Line
Loopback
Payload
FIFO
DS1/E1 Framer Block
Off-Line
Framer
The CX29503 has 84 DS1/E1 Framer blocks; there are 28 DS1/E1 Framer blocks per
Mapping/MUXing module. DS1/E1 framers operate when the device is configured to
one of the following modes:
In these modes, 28 DS1 or up to 21 E1 payloads and overhead data can be terminated
at the TSB Interface module for transmission to an external HDLC controller. DS1/E1
framing detection/insertion, performance monitoring, alarm generation, overhead bit
processing, loopback capability, and unchannelized DS1/E1 testing are supported
within this block.
The DS1/E1 framer core is shown in
Mindspeed’s CN8398 DS1/E1 framer device, software and functional compatibility is
maintained.
Channelized DS3/E3
DS1/E1 mapped VT/VC
Insertion
Framing
Performance
Transmitter
Time Base
Time Base
Receiver
Monitor
Mindspeed Technologies™
Insertion
Alarm
Preliminary Information
Loop Code
Detection
PRBS
Loop Code
Detection
PRBS
Receiver
Handler
Transmitter
BOP
Figure
BOP
2-10. Because the core is compatible with
Data LInk
Controller
Transmitter
Receiver
Controller
Data Link
MOP/BOP
Arbitration
Insertion
AIS
Extraction
Overhead
Overhead
Insertion
Functional Description
Data
Data
EXT_DSICLK
EXT_E1CLK
TXCLKO
TFSYNC
RDATAO
RDLO
RDLCKO
RFSYNC
TDLCKO
TDLI
TXCAT1
100702_018
2
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