cx29503 Mindspeed Technologies, cx29503 Datasheet - Page 249

• Manufacturer Part Number: cx29503
• Description: Cx29503 Broadband Access Multiplexer Data Sheet
• Manufacturer: Mindspeed Technologies

CX29503 Data Sheet
AutoRAI
ExtFEBE/Cj
ExtCP/TR
ExtFEAC/PD
ExtDat
29503-DSH-002-B
DLMod[0] controls the reserved C-bits (C12, Cb2, Cb6, Cb7) generation. When cleared, these
bits are automatically generated as all 1s. This bit must not be set because the CX29503 does
not support the transfer of the reserved C bits over the TSB interface.
Automatic RAI/RDI generation control—Set to enable automatic generation of the RAI or
RDI alarm in response to a fault detection. When set, an automatic assertion of RAI in E3-
G.751 mode occurs once the receiver detects an LOS or OOF condition. The automatic
assertion continues as long as one or more of these conditions is valid. The TxAlm[1] bit in the
Mode Control register still affects RAI/RDI generation in E3 mode while this bit is set. When
clear, RAI/RDI generation occurs due to the TxAlm[1] bit in the Mode Control register, and
there is no automatic generation.
External FEBE/Justification Control—Must be cleared because the CX29503 does not support
the insertion of FEBE or justification control bits via the TSB interface.
External CP/Timing Marker/SSM Control—In DS3-C Bit Parity mode, this bit must be
cleared because the CX29503 does not support the insertion of CP bits or TR byte via TSB
interface mode. In DS3-M13/M23 and E3-G.751 modes, this bit has no effect.
External FEAC/Payload Dependent/Multiframe Indicator Field Control—In DS3-C Bit Parity
mode, this bit must be cleared because the CX29503 does not support the insertion of an
FEAC channel via the TSB interface. When this bit is cleared, the FEAC channel is inserted
through a programmable register (Transmit FEAC Channel Byte) in DS3-C Bit Parity mode. In
DS3-M13/M23 and E3-G.751 modes, this bit has no effect.
External Data Control—Set to enable all overhead bits to be inserted via the data stream.
When set, this bit overrides the rest of the control bits in this register. It disables internal
generation of overhead bits (automatic or through programmable registers) and forces the chip
to use the overhead bits inserted in the data stream of the Transmit Overhead Insertion2
Control register. When clear, overhead configuration is determined by the rest of the control
bits as described above. This bit affects all modes. Setting of TxAlm[1:0] bits is effective even
during ExtDat = 1.
DS3-C Bit Parity
NOTE:
Mindspeed Technologies™
This bit has no effect in DS3 mode. Generation of an RAI alarm in DS3 mode is
controlled only by TxAlm bits.
Preliminary Information
Register Description
8
-
119