cx29503 Mindspeed Technologies, cx29503 Datasheet - Page 290

• Manufacturer Part Number: cx29503
• Description: Cx29503 Broadband Access Multiplexer Data Sheet
• Manufacturer: Mindspeed Technologies

Register Description
8.4.4.1
The register offsets for each channel are listed in
Reset State
Lpbk_IE
8-160
—
7
0x00
Interrupt Enable for DS1/E1 MUX Loopback—When set to 1, allows interrupt due to
detection of the DS1/E1 loopback command in the DS2 stream for this channel. When cleared
to 0, a status bit is set when the event is detected but the interrupt will not be generated.
—
6
DS1/E1 MUX Channel 1–28 Receive Interrupt Enable
Table 8-50. Register Offsets—DS1/E1 MUX Channel 1–28 Receive Interrupt Enable
Offset (Hex)
0x550D
0x551D
0x552D
0x553D
0x554D
0x555D
0x556D
0x5505
0x5515
0x5525
0x5535
0x5545
0x5555
0x5565
—
5
Mindspeed Technologies™
Preliminary Information
—
4
Table
Channel
8-50.
10
11
12
13
14
1
2
3
4
5
6
7
8
9
—
3
Offset (Hex)
—
2
0x557D
0x558D
0x559D
0x55AD
0x55BD
0x55CD
0x55D5
0x55DD
0x5575
0x5585
0x5595
0x55A5
0x55B5
0x55C5
—
1
CX29503 Data Sheet
Channel
29503-DSH-002-B
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Lpbk_IE
0