cx29503 Mindspeed Technologies, cx29503 Datasheet - Page 23
cx29503
Manufacturer Part Number
cx29503
Description
Cx29503 Broadband Access Multiplexer Data Sheet
Manufacturer
Mindspeed Technologies
Datasheet
1.CX29503.pdf
(388 pages)
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Tables
29503-DSH-002-B
Table 1-1.
Table 1-2.
Table 1-3.
Table 1-4.
Table 1-5.
Table 1-6.
Table 1-7.
Table 1-8.
Table 2-1.
Table 2-2.
Table 2-3.
Table 2-4.
Table 2-5.
Table 2-6.
Table 2-7.
Table 2-8.
Table 2-9.
Table 2-10.
Table 2-11.
Table 2-12.
Table 4-1.
Table 4-2.
Table 4-3.
Table 4-4.
Table 4-5.
Table 4-6.
Table 4-7.
Table 4-8.
Table 4-9.
Table 4-10.
Table 4-11.
Table 4-12.
Table 4-13.
Table 4-14.
Table 5-1.
Table 6-1.
Number of Framer Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
SI-Bus Line Interface Supported Through-Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
Serial Line Interface Supported Through-Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
SI-Bus Line Interface Supported Through-Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
Serial Line Interface Supported Through-Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
Pin Assignments (1 of 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13
Pin Type Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17
Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17
VT Overhead Bytes and Associated Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
VT Start/End Events and Associated Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
VT One “Shot Events” and Associated Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
DS1 Mode In-Frame and Out-of-Frame Criteria . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24
E1 Mode In-Frame and Out-of-Frame Criteria . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24
TSB Bandwidths. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-33
TSB Data Paths and Bus Rates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-36
Mapping of CX29503 Data Paths To and From TSB Time Slots . . . . . . . . . . . . . . . . . . . . . 2-38
Mapping of Unchannelized STS-1 To and From TSB Time Slots . . . . . . . . . . . . . . . . . . . . 2-39
Mapping of Unchannelized DS3 To and From TSB Time Slots in SI-Bus Mode . . . . . . . . . 2-39
Mapping of Unchannelized E3 To and From TSB Time Slots in SI-Bus Mode. . . . . . . . . . . 2-40
Mapping of Data To and From Overhead TSB Time Slots . . . . . . . . . . . . . . . . . . . . . . . . . . 2-43
SI-Bus Clock Sources in SI-Bus Interface Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
DS3 Clock Sources and Configuration Bits in SI-Bus Interface Mode . . . . . . . . . . . . . . . . . 4-4
E3 Clock Sources and Configuration Bits in SI-Bus Interface Mode . . . . . . . . . . . . . . . . . . . 4-5
DS1 Clock Sources and Configuration Bits in SI-Bus Interface Mode . . . . . . . . . . . . . . . . . 4-5
E1 Clock Sources and Configuration Bits in SI-Bus Interface Mode . . . . . . . . . . . . . . . . . . . 4-6
DS3 Clock Sources and Configuration Bits in Serial DS3 Interface Mode . . . . . . . . . . . . . . 4-7
DS1 Clock Sources and Configuration Bits in Serial DS3 Interface Mode . . . . . . . . . . . . . . 4-7
E3 Clock Sources and Configuration Bits in Serial E3 Interface Mode . . . . . . . . . . . . . . . . . 4-8
E1 Clock Sources and Configuration Bits in Serial E3 Interface Mode . . . . . . . . . . . . . . . . . 4-8
Payload TSB Clock Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10
Overhead TSB Clock Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10
CSP and Microprocessor Clock Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
DS1/E1 System and DS1/E1 Microprocessor Clock Configurations . . . . . . . . . . . . . . . . . . 4-12
Selections for the One Hertz Clock Source and CLK_1HZ Pin . . . . . . . . . . . . . . . . . . . . . . 4-13
Clock Sources for DS1/E1 Loopback Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
STS-1 Path Conditioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
Mindspeed Technologies™
Preliminary Information
xxiii
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