cx29503 Mindspeed Technologies, cx29503 Datasheet - Page 168

• Manufacturer Part Number: cx29503
• Description: Cx29503 Broadband Access Multiplexer Data Sheet
• Manufacturer: Mindspeed Technologies

Register Description
0x16—External Data Link Bit (DL3_BIT)
The DL3_BIT works in conjunction with the DL3_TS register [addr: 0x15] to access the overhead Sa data from
the TSB overhead channel.
Reserved bits should be written to 0.
DL3_BIT[4:0]
Table 8-11. External Data Link Sa Byte Selection
8-38
RESERVED
Mode
E1
T1
7
DL3_BIT[4]
RESERVED
External Data Link Sa Byte Select—In E1 mode, if DL3EN is set and TS[0] is cleared in the
DL3_TS [addr: 0x15], one or more Sa data bits are selected to be passed from and to the TSB
overhead bus. In T1 mode, DL3_BITS[4:0] has no effect.
1
x
x
x
x
x
6
DL3_BIT[3]
RESERVED
5
x
x
x
x
1
x
Mindspeed Technologies™
DL3_BIT[4]
DL3_BIT[2]
Preliminary Information
4
x
x
x
1
x
x
DL3_BIT[3]
DL3_BIT[1]
3
x
x
1
x
x
x
DL3_BIT[2]
DL3_BIT[0]
2
1
x
x
x
x
x
DL3_BIT[1]
ESF FDL data
Sa 8 data selected
Sa 7 data selected
Sa 6 data selected
Sa 5 data selected
Sa 4 data selected
1
CX29503 Data Sheet
29503-DSH-002-B
Data
DL3_BIT[0]
0