cx29503 Mindspeed Technologies, cx29503 Datasheet - Page 244

• Manufacturer Part Number: cx29503
• Description: Cx29503 Broadband Access Multiplexer Data Sheet
• Manufacturer: Mindspeed Technologies

Register Description
0x5225—Feature2 Control Register
On the CX29503, the system side of the DS3/E3 framer can connect to either the TSB interface or the M13
block.
Default after rest:
Direction:
Modification:
TxLOS
TxOvhMrk
TXSYOut
TXSYIn
TxInvClk
LTxCkRis
8-114
Reserved
7
Reserved
01(h)
Read/Write
Bit 5, dynamic; bits 0–4, static
Transmit LOS—This bit, while set, results in the generation of all 0s (LOS) on the transmit
line side. Setting this bit overrides any other programmed/inserted payload and overhead
pattern with 0s.
Transmit Overhead Bits Mark—This bit controls the behavior of the TXSY signal when
programmed to be driven as an output. When set, TXSY marks the bit positions of all overhead
bits. When cleared, TXSY marks the beginning of a new frame.
TXSY Signal Output Control—This bit determines if the TXSY signal is an output of the
framer block. When set, this signal is an output, i.e., the transmitter circuit generates its own
frame synchronization mechanism and signals the frame start or the overhead bit positions
(according to TxOvhMrk bit) on the TXSY signal to the system. When cleared, TXSY can be
an input or undefined according to the value of the TXSYIn bit in this register.
TXSY Signal Input Control—This bit determines if the TXSY signal is an input of the framer
block. When set, this signal is an input, i.e., the system generates a synchronization pulse and
the transmitter circuit acts according to it. When cleared, TXSY can be an output or undefined
according to the value of the TXSYOut bit in this register.
Transmit System Side Inverted Clocks—This bit controls the polarity of TXGAPCK and
TEXTCK output clocks. When the bit is cleared, TXGAPCK and TEXTCK rising edges are
derived from TXCKI falling edge. In this mode, both clock gaps are active-low. When this bit
is set, TXGAPCK and TEXTCK are inverted, hence TXGAPCK and TEXTCK falling edges
are derived from TXCKI falling edge. In this mode, both clock gaps are active high.
LIU Transmit Clock Polarity Control—Used to define the TCLKO edge upon which the
transmitter output data (on TXPOS, TXNEG signals) is sampled by the LIU. When set, the
data is clocked out by the chip on the falling edge of TCLKO. It is sampled by the LIU on the
rising edge of TCLKO. When cleared, the data is clocked out by the chip on the rising edge of
TCLKO; therefore, it is sampled by the LIU on the falling edge of TCLKO.
During and after reset, TXSY drives high Z, and is neither in output state nor in input state.
During and after reset, TXSY drives high Z, and is neither in output state nor in input state.
6
NOTE:
NOTE:
TxLOS
5
Mindspeed Technologies™
TXSYOut must be set in the CX29503.
TXSYIn must be cleared in the CX29503.
TxOvhMrk
Preliminary Information
4
TXSYOut
3
TXSYIn
2
TxInvClk
1
CX29503 Data Sheet
29503-DSH-002-B
LTxCkRis
0