cx29503 Mindspeed Technologies, cx29503 Datasheet - Page 243

• Manufacturer Part Number: cx29503
• Description: Cx29503 Broadband Access Multiplexer Data Sheet
• Manufacturer: Mindspeed Technologies

CX29503 Data Sheet
0x5224—Feature1 Control Register
On the CX29503, the line side of the DS3/E3 framer can connect to either the serial line side interface or the
SONET/SDH block. If the interface to the SONET/SDH block is used, then the NRZ mode bit must be set high.
Default after reset:
Direction:
Modification:
TxAMI
RxAMI
NRZMod
FEBEC/PT[1:3]
29503-DSH-002-B
TxAMI
7
RxAMI
07(h)
Read/Write
Bits 0–2, dynamic; bits 5–7, static
Transmit AMI mode—Set high to enable AMI line coding on TXPOS and TXNEG (no B3ZS/
HDB3 encoding/decoding). When cleared, B3ZS/HDB3 line coding is used on these signals.
This bit is effective only when the NRZMod bit, in this register, is cleared (see
Receive AMI mode—Set high to enable AMI line coding on RXPOS and RXNEG (no B3ZS/
HDB3 encoding/decoding). When cleared, these signals use B3ZS/HDB3 line coding. This bit
is effective only when the NRZMod bit in this register is cleared (see
NRZ mode—Set high to disable bipolar (B3ZS/HDB3 or AMI) encoding/decoding and
provide a unipolar NRZ line code on TXPOS, TXNEG, RXPOS, and RXNEG. Setting this bit
disables the encoder/decoder circuits and bypasses them. The unipolar output appears at the
TXPOS signal while the TXNEG signal is continuously low and the clock is available on the
TCLKO signal. The unipolar input should appear on RXPOS, while RXNEG can be tied to the
LCV output of the LIU and used as an increment control of the LCV counter.
FEBE Pattern/Payload Type Bit Field—In DS3 mode the 3-bit sequence that is sent when a
FEBE indication is transmitted in C-bit parity mode. This pattern is automatically transmitted
when the ExtFEBE/Cj bit in the Transmit Overhead Insertion 1 control register is cleared and
the receiver detects a framing or path parity error. The pattern must be anything other than all
1s to indicate a the FEBE to the far end. An all 1s pattern will disable FEBE transmission and
should not be used for any other purpose.
In both modes, the FEBEC/PT[1] bit is transmitted first and the FEBEC/PT[3] bit is
transmitted last. In both modes, writing a new value to this byte or bit takes effect only starting
from the next transmitted frame.
In DS3-M13/M23 and E3-G.751 modes, this field has no effect.
6
Table 8-45. DS3/E3 Framer Line Side Configurations
NRZMod
NRZMod
0
0
0
0
1
5
RxAMI
Mindspeed Technologies™
X
X
X
0
1
Reserved
4
Preliminary Information
TxAMI
X
X
X
0
1
B3ZS/HDB3 encoded data on RXPOS, RXNEG
AMI encoded data on RXPOS, RXNEG
B3ZS/HDB3 encoded data on TXPOS, TXNEG
AMI encoded data on TXPOS, TXNEG
NRZ data on TXPOS, RXPOS; TXNEG is set to 0; RXNEG is used as
an LCV input from the LIU (if unused, should be tied low)
Reserved
3
FEBEC/PT[1]
2
Configuration
FEBEC/PT[2]
Table
1
8-45).
Register Description
Table
FEBEC/PT[3]
8-45).
0
8
-
113