cx29503 Mindspeed Technologies, cx29503 Datasheet - Page 138

• Manufacturer Part Number: cx29503
• Description: Cx29503 Broadband Access Multiplexer Data Sheet
• Manufacturer: Mindspeed Technologies

Register Description
8.2
The TSB interface occupies offsets 0x100–0x1FF within each mapper/multiplexer block.
Top Level TSB register map. The address of each register is the offset from the start address of the block of
registers assigned to the TSB module.
Table 8-2. Top Level—TSB Module Register Map
0x0100 to 0x01EC—Test Registers
Reserved for TSB module testing.
0x01ED – Unframed Link Control Register 1
8-8
01ED–01FC
0100–01EC
Reserved
Offset
01FB
01FC
01FD
01F1
01F2
01F3
01F4
01F5
01F6
01F7
01F8
01F9
01FA
01FE
01FF
L8
7
7
Type
Reserved
R/W
R/W
R/W
R/W
R/W
R/W
—
W
R
R
R
R
R
R
R
R
R
L7
Time Slot Bus (TSB) Interface
6
6
Reset State: 0x00
Clear on Read
Reserved
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
—
L6
5
5
Mindspeed Technologies™
Test Registers
Unframed Link Control Registers
Flush FIFOs
TSB FIFO Interrupt Status Register
TSB FIFO Interrupt Enable Register
Overflow Transmit Payload FIFO Number Status Register
Underflow Transmit Payload FIFO Number Status Register
Overflow Receive Payload FIFO Number Status Register
Underflow Receive Payload FIFO Number Status Register
Overflow Transmit Overhead FIFO Number Status Register
Underflow Transmit Overhead FIFO Number Status Register
Overflow Receive Overhead FIFO Number Status Register
Underflow Receive Overhead FIFO Number Status Register
TSB Module Operation Control Register
Reserved
Framer Set Configuration Register 1
Framer Set Configuration Register 2
Reserved
L5
4
Preliminary Information
4
L4
Reserved
3
Register Description
3
L3
2
Reserved
2
L2
1
Reserved
Table 8-2
1
CX29503 Data Sheet
29503-DSH-002-B
L1
0
shows the
Reserved
Default
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x40
0x00
0x00
0x00
0