cx29503 Mindspeed Technologies, cx29503 Datasheet - Page 203

• Manufacturer Part Number: cx29503
• Description: Cx29503 Broadband Access Multiplexer Data Sheet
• Manufacturer: Mindspeed Technologies

CX29503 Data Sheet
0xA5—DL1 Bit Enable (DL1_BIT)
DL1_BIT[7:0]
0xA6—DL1 Control (DL1_CTL)
Unused bits are reserved and should be written to 0.
TDL1_RPT
29503-DSH-002-B
DL1_BIT[7]
—
7
7
DL1_BIT[6]
DL1 Bit Select—Works in conjunction with DL1_TS [addr: 0A4] to select one or more time
slot bits for data link input and output. Any combination of bits may be enabled by writing the
corresponding DL1_BIT active (high). The LSB enables the first bit transmitted or received,
and the MSB enables the eighth bit transmitted or received. DL1_BIT has no effect when
DL1_TS selects T1 F-bits.
Circular Transmit Buffer Enable—the Processor can fill the transmit FIFO
[TDL1; addr: 0AD] with up to 64 bytes (Pack6 or Pack8 bits/byte) of unformatted data to be
sent repeatedly. While TDL1_RPT is active-high, data written to TDL1 is held until the
processor writes an End-Of-Message (EOM) [TDL1_EOM; addr: 0AC]. After TDL1_EOM is
written, the transmitter waits for the beginning of the next output multiframe (based on the
selected transmit framing mode) before sending the first byte of the circular buffer.
Subsequent bytes are output in the selected time slot and overhead bits, and will continue to
wrap around (recirculate) from the buffer until the processor writes new buffer data and
another TDL1_EOM. This allows the processor to send multiframe aligned data patterns in
ESF, SF, FAS, or MFAS overhead bits.
—
6
6
0 = disable data link bit
1 = enable data link bit
0 = normal transmit FIFO
1 = enable circular transmit buffer
DL1_BIT[5]
—
5
5
Mindspeed Technologies™
DL1_BIT[4]
TDL1_RPT
Preliminary Information
4
4
DL1_BIT[3]
DL1[1]
3
3
DL1_BIT[2]
DL1[0]
2
2
DL1_BIT[1]
TDL1_EN
1
1
Register Description
DL1_BIT[0]
RDL1_EN
0
0
8
-
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