cx29503 Mindspeed Technologies, cx29503 Datasheet - Page 111

• Manufacturer Part Number: cx29503
• Description: Cx29503 Broadband Access Multiplexer Data Sheet
• Manufacturer: Mindspeed Technologies

CX29503 Data Sheet
4.4
Table 4-6. DS3 Clock Sources and Configuration Bits in Serial DS3 Interface Mode
Table 4-7. DS1 Clock Sources and Configuration Bits in Serial DS3 Interface Mode
29503-DSH-002-B
DS3 Receive Framer Line
Clock
(LINECLK)
DS3 Transmit Framer Line
Clock (m13_clk_txlineo)
FOOTNOTE:
(1)
DS1 Receive Framer Line
Clock (RCKI)
DS1 Transmit Framer System
Clock (TSBCKI) and Line
Clocks (fr1_txclk_m13 and
fr1_clk_tx)
FOOTNOTE:
(1)
upl3txclkset[1:0] is located in the M13/E13 System Control register
TXE3_CLKSEL is located in the Clock Configuration register
XMTR_SEL_n[1:0] is located in Framer Control Registers 1 and 2
RCVR_SEL is located in Framer Control Register 1
FLOOP is located in the Loopback Configuration register
Description
Description
Serial DS3 Interface Mode
In the serial DS3 interface mode, typically, the line side of the device is connected to
an external LIU.
mode is enabled by setting the CK_SRC[1:0] pins to 0
Table 4-7
path is unchannelized DS3, then all DS1 framers can be disabled by setting RABORT
in the Receiver Configuration register
44.736
44.736
(MHz)
(MHz)
Freq.
Freq.
1.544
1.544
lists the configuration settings depending on the timing mode. If the data
Mindspeed Technologies™
Table 4-6
System or Looped
System
Looped
System or Looped
System
Looped
Preliminary Information
(Section
Timing Mode
Timing Mode
(Section
lists the external clocking required in this mode. This
8.3.1).
(Section
8.3.2.4).
(Section
(Section
8.8).
(Section
RLINECLK
CLK_TXDS3
LINECLK
RXCKI
M13/E13 Block
CLK_TXDS1
Receive DS1 Clock
Clock Source
Clock Source
8.3.1).
8.4.1).
8.3.2.5).
×
Clock Sources and Clock Configurations
2 or 0
upl3txclkset[1:0] = 0 × 1
TXE3_CLKSEL = 0 × 0
upl3txclkset[1:0] = 0 × 0
TXE3_CLKSEL = Don't Care
upl3txclkset[1:0] = 0 × 2 or
0 × 3
TXE3_CLKSEL = Don't Care
RCVR_SEL = 0 × 0
FLOOP = 0 × 0
XMTR_SEL_n[1:0] = 0 × 00
XMTR_SEL_n[1:0] = 0 × 1X
Configuration Bits
Configuration Bits
×
3.
—
(1)
(1)
4
-
7