cx29503 Mindspeed Technologies, cx29503 Datasheet - Page 258

• Manufacturer Part Number: cx29503
• Description: Cx29503 Broadband Access Multiplexer Data Sheet
• Manufacturer: Mindspeed Technologies

Register Description
Figure 8-5. DS3/E3 Framer Interrupt Structure
Value after reset:
Direction:
Value after enable:
TxDLFEACItr
RxDLltr
RxFEACltrs
AlarmEndItr
AlarmStrtItr
Ctrltr
8-128
Reserved
7
Top Level
2nd Level
Registers
3rd Level
Enable
Reserved
00(h)
Read only
Unaffected (affected indirectly by other registers)
Transmit Data Link/FEAC Interrupt Source—Set if one or more of the interrupt-related active
status bits in the Transmit Data Link FEAC Status register are high. Cleared when the bits
related to interrupt activation in the Transmit Data Link FEAC Status register or their interrupt
masks are low.
Receive Data Link Interrupt Source—Set if one or more on the interrupt-related active status
bits in the Receive Data Link Status register are high. Cleared when the bits related to interrupt
activation in the Receive Data Link Status register or their interrupt masks are low.
Receive FEAC Interrupt Source —Set if one or more of the interrupt-related active status bits
in the Receive FEAC Status register are high. Cleared when the bits related to interrupt
activation in the Receive FEAC Status register or their interrupt masks are low.
Alarm End Interrupt2 Source—Set if one or more of the active status bits in the Alarm End
Interrupt Status register are high. Cleared when the bits related to interrupt activation in the
Alarm End Interrupt Status register or their interrupt masks are low.
Alarm Start Interrupt Source—Set if one or more of the active status bits in the Alarm Start
Interrupt Status register are high. Cleared when the bits related to interrupt activation in the
Alarm Start Interrupt Status register or their interrupt masks are low.
Counter Interrupt Source—Set if one or more of the active status bits in the Counter Interrupt
Status register are high. Cleared when the bits related to interrupt activation in the Counter
Interrupt Status register or their interrupt masks are low.
6
Tx FEAC
TDL and
(x248)
x22D)
(x226
ISR
and
TxDLFEACItr
5
(x24B)
(x231)
RDL
Mindspeed Technologies™
ISR
Preliminary Information
RxDLltr
Top Level Interrupt Status Register
Interrupt Request Register (x241)
4
Rx FEAC
(x251)
(x226)
ISR
RxFEACltrS
3
(x244)
(x223)
Alarm
End
ISR
AlarmEndItr
2
(x243)
(x222)
Alarm
Start
ISR
AlarmStrtItr
1
CX29503 Data Sheet
Counter
29503-DSH-002-B
(x242)
(x221)
ISR
Ctrltr
0
100702_042