cx29503 Mindspeed Technologies, cx29503 Datasheet - Page 255

• Manufacturer Part Number: cx29503
• Description: Cx29503 Broadband Access Multiplexer Data Sheet
• Manufacturer: Mindspeed Technologies

CX29503 Data Sheet
0x522F and 0x5230—Transmit Data Link Message Byte
(Lower Address and Higher Address)
Default after reset:
Direction:
Modification:
TxDLMsg[7:0]
0x5231—Receive Data Link Control Register
The Receive Data Link Control register enables operation of the receiver terminal data link circuit, defines the
FCS mode, and enables interrupt assertion due to data link events.
Default after reset:
Direction:
Modification:
NRDL
RxOVRIE
RxMsgIE
RxNFIE
29503-DSH-002-B
TxDLMsg [7]
Reserved
7
7
TxDLMsg [6]
Reserved
Undefined
Read/Write
Dynamic
Transmit DL Message byte—This byte is loaded with data to be written into the data link FIFO
buffer, and is later transmitted by the data link transmitter circuit. Two addresses are allocated
for this register. During the entire message, excepting the last byte of the message, the lower
address is used to access this register. When the last byte of the message is written to this
register, the higher address is used. Using the higher address indicates the end of the message
to the transmitter circuit.
The TxDLMsg[0] bit is transmitted first and the TxDLMsg[7] bit is transmitted last. Reading
this register causes latching of the content of the FIFO stage pointed by the Transmit DL Read
Pointer into this register.
00(h)
Read/Write
Bits 0, 2–4—dynamic; bits 1, 5—DL-static
NR Byte over the DL—This bit is effective only in E3-G.832 mode and is reserved for the
CX29503 application and must be maintained low.
Receive DL FIFO Overrun Interrupt Enable—Set to enable interrupt assertion due to data link
FIFO overrun error.
Receive DL Message Interrupt Enable—Set to enable interrupt assertion due to a message
received event.
Receive DL FIFO Near-Full Interrupt Enable—Set to enable interrupt assertion due to the
FIFO near-full event.
6
6
NOTE:
TxDLMsg [5]
NRDL
5
5
Mindspeed Technologies™
Reserved bits in control registers must be set to 0.
TxDLMsg [4]
RxOVRIE
Preliminary Information
4
4
TxDLMsg [3]
RxMsgIE
3
3
TxDLMsg [2]
RxNFIE
2
2
TxDLMsg [1]
RxFCSEn
1
1
Register Description
TxDLMsg [0]
RxDLEn
0
0
8
-
125