cx29503 Mindspeed Technologies, cx29503 Datasheet - Page 103

• Manufacturer Part Number: cx29503
• Description: Cx29503 Broadband Access Multiplexer Data Sheet
• Manufacturer: Mindspeed Technologies

CX29503 Data Sheet
3.4
29503-DSH-002-B
Command and Status Processor (CSP)
The CSP is a module in the CX29503 device which internally automates functions
typically handled by the host processor. Typical functions automated include device
status retrieval, device configuration, performance monitoring of all DS1, M13/E13,
DS3, and SONET/SDH blocks, and automatic response to network events and alarms.
Figure 3-2
The CSP acts as an interface between the internal registers and the host processor via
the TSB Interface block. The CSP communicates with the host processor via HDLC-
type packets containing commands, responses, and status information. For testing and
development purposes, a local host can access the CSP using the Parallel
Microprocessor interface. The CSP communicates with the internal registers by using
the communication block that is also used by the parallel microprocessor interface.
Because it processes network events internally to the device, the CSP significantly
reduces real-time requirements of the host processor. The CSP consists of an interrupt
controller, a Micro-Coded State Machine (MCSM), microcode RAM, MCSM control
registers, transmit and receive FIFO buffers, an HDLC controller, and an external
microprocessor override interface. Each of the internal blocks interface with the CSP
via the interrupt controller and a microprocessor-style address and data link. The CSP
monitors interrupts from each of the internal blocks and processes requests as
necessary using either a round-robin or priority-based scheduling mechanism as
defined by the microcode and MCSM control registers. When a block has been
selected for processing, the CSP either generates a message and transmits it to the host
processor via the transmit FIFO, or it reads the appropriate registers from the selected
block and makes a decision of the correct action to take.
Applications that use the EBUS interface must disable the CSP with these 3 steps:
NOTE:
1.
2.
3.
NOTE:
Request a CSP halt by setting HALT_REQ in register RUN_CONFIG on each
slice.
Within 5 seconds, disable the watch dog timer by writing 0 to register WD_CTL.
Check the RUN_CONFIG register. If HALT_REQ and HALT_ACTIVE are
cleared, then repeat step 1. If HALT_REQ and HALT_ACTIVE are set, then
continue normal processing.
shows a block diagram of the CSP.
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Because both the CSP and a local host processor access the common set of internal
registers, software should configure the device such that only one of the processors
is responsible for reading clear-on-read registers such as interrupt status registers.
Because the CSP uses a free running 5-second timer, steps 1 and 2 can occur
anywhere in that 5-second window. Therefore, step 3 is required to guarantee that
steps 1 and 2 worked.
Preliminary Information
Parallel Microprocessor Interface
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