cx29503 Mindspeed Technologies, cx29503 Datasheet - Page 166

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cx29503

Manufacturer Part Number
cx29503
Description
Cx29503 Broadband Access Multiplexer Data Sheet
Manufacturer
Mindspeed Technologies
Datasheet
Register Description
8.3.2.4
0x14—Loopback Configuration Register (LOOP)
Unused and reserved bits should be written to 0.
UPLOOP
LLOOP
FLOOP
8-36
7
Enable Unchannelized Payload Loopback—This loopback only loops the received payload
data back to the transmitter. The overhead data is continuously sourced from the transmitter.
Because the transmitting data is driven by the transmit clock, the received payload data passes
through a 64-bit FIFO to accommodate receiver jitter (mainly introduced by the VT mapper).
Enable Line Loopback—Received data from the line side is internally connected to transmit
side. The receive clock (RCKI) is internally connected to the transmit clock output (TCKO).
LLOOP and FLOOP can be active simultaneously to support both line and network loopbacks
at the same time.
Enable Local Framer Loopback—Transmit line data is internally connected to the receive line
input. Clock switching is automatic during FLOOP Loopback mode.
6
Configuration Registers
0 = no loopback
1 = unchannelized payload loopback
0 = no loopback
1 = unchannelized payload loopback
0 = no loopback
1 = unchannelized payload loopback
5
Mindspeed Technologies™
Preliminary Information
4
UPLOOP
3
LLOOP
2
FLOOP
1
CX29503 Data Sheet
29503-DSH-002-B
0

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