cx29503 Mindspeed Technologies, cx29503 Datasheet - Page 110
cx29503
Manufacturer Part Number
cx29503
Description
Cx29503 Broadband Access Multiplexer Data Sheet
Manufacturer
Mindspeed Technologies
Datasheet
1.CX29503.pdf
(388 pages)
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Clock Sources and Clock Configurations
Table 4-5. E1 Clock Sources and Configuration Bits in SI-Bus Interface Mode
4-6
E1 Receive Framer Line Clock
(RCKI)
E1 Transmit Framer System
(TSBCKI) and Line Clocks
(fr1_txclk_m13 and
fr1_clk_tx)
FOOTNOTE:
(1)
XMTR_SEL_n[1:0] is located in Framer Control register 1 and 2
RCVR_SEL is located in Framer Control register 1
FLOOP is located in the Loopback Configuration register
Description
(MHz)
Freq.
2.048
2.048
Mindspeed Technologies™
System or Looped
System
Looped
Preliminary Information
(Section
Timing Mode
(Section
8.3.1).
(Section
8.3.2.4).
M13/E13 Block
SONET Block
CLK_TXE1
Receive E1 Clock
8.3.1).
Clock Source
RCVR_SEL = 0 × 0
FLOOP = 0 × 0
RCVR_SEL = 0 × 1
FLOOP = 0 × 0
XMTR_SEL_n[1:0] = 0 × 01
XMTR_SEL_n[1:0] = 0 × 2
or 0 × 3
Configuration Bits
CX29503 Data Sheet
29503-DSH-002-B
(1)
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