cx29503 Mindspeed Technologies, cx29503 Datasheet - Page 246

• Manufacturer Part Number: cx29503
• Description: Cx29503 Broadband Access Multiplexer Data Sheet
• Manufacturer: Mindspeed Technologies

Register Description
RxFEACIE
0x5227—Feature4 Control Register
This control register has an effect only in E3-G.832 mode. Because the CX29503 does not support E3-G.832
mode, this register is reserved and must be maintained at its initial value of 0x00.
Default after reset:
SSMEn
SSM[1]/TM
SSM[2:4]
MAPD[1:2]
0x5228—Feature5 Control Register
Default after rest:
Direction:
Modification:
RxAutoAll
RefrmStp
8-116
RxAutoAll1
Reserved
7
7
RefrmStp
Receive FEAC Interrupt Enable—A control bit that allows interrupts from the FEAC receiver
when in DS3-C Bit Parity mode. When a legal code word is detected by the receiver, the
interrupt is asserted. The associated interrupt status is reported in the RxFEACItr bit in the
Receive FEAC Interrupt Status register [addr: 251].
00(h)
SSM Mode Enable
SSM MSB/Timing Marker Bit Field
SSM Bit Field
Payload Dependent Field in MA Byte
00(h)
Read/Write
Bits 4–6, dynamic; bits 0–3, 7-static
Receive Automatic All 1s on Data Stream—Set to enable automatic generation of an all-1s
stream on RXDAT signal in response to a fault detection. When set and LOS, OOF, AIS, or
Idle are detected in DS3 mode or LOS, OOF, or AIS are detected in E3 mode, the data received
on RXPOS, RXNEG is presented to the receiver circuit, but is not present on RXDAT signal. It
is overwritten by an all-1s stream. The automatic all-1s assertion continues as long as one or
more of these conditions is valid.
When clear, all 1s sequences on the RXDAT signal occurs due to the RxAll1 bit in this register.
RxAll1 and RxAIS bits in this register have precedence over this bit and affect the RX data
stream.
Reframe Mechanism Stop—This bit controls the behavior of the frame-search mechanism.
When this bit is set (=1), no frame-search is conducted (regardless of OOF status); when it has
been cleared (0 is written over a previous 1), frame-search resumes, shifted forward by 1 bit
from the current frame position, until a new framing is located. When it is cleared (=0),
searching occurs in response to an OOF status.
SSMEn
6
6
NOTE:
SSM[1]/TM
RxAIS
5
5
Mindspeed Technologies™
To produce a “forced reframe”, the microprocessor will usually need 2 write cycles,
the first to write 1 to the bit, the next to write 0 to it.
SSM[2]
RXAll1
Preliminary Information
4
4
RxOvhMrk
SSM[3]
3
3
RxFIFEn
SSM[4]
2
2
MAPD[1]
RxInvClk
1
1
CX29503 Data Sheet
29503-DSH-002-B
LRxCkRis
MAPD[2]
0
0