cx29503 Mindspeed Technologies, cx29503 Datasheet - Page 181

• Manufacturer Part Number: cx29503
• Description: Cx29503 Broadband Access Multiplexer Data Sheet
• Manufacturer: Mindspeed Technologies

CX29503 Data Sheet
8.3.2.6
If the counter overflow interrupt [IER4; addr: 00F] is enabled for the respective Performance Monitoring
counter, the counter is allowed to roll over after reaching its maximum count value. If the overflow interrupt is
disabled, the counter will hold its maximum value upon saturation. Refer also to LATCH [addr: 046] for a
description of one-second latched counter operation. The processor must read the LSB before reading the MSB
of each multibyte counter.
0x50—Framing Bit Error Counter LSB (FERR)
FERR[7:0]
0x51—Framing Bit Error Counter MSB (FERR)
If LATCH_CNT [addr: 046] is inactive, reading FERR [addr: 051] clears the entire FERR[11:0] count value.
FERR[11:8]
0x52—CRC Error Counter LSB (CERR)
CERR[7:0]
0x53—vCRC Error Counter MSB (CERR)
If LATCH_CNT [addr: 046] is inactive, reading CERR [addr: 053] clears the entire CERR[9:0] count value.
CERR[9:8]
29503-DSH-002-B
CERR[7]
FERR[7]
15
15
7
0
7
0
Ft/Fs/FPS/FAS Error Count
Ft/Fs/FPS/FAS Error Count
CRC6/CRC4 Error Count
CRC6/CRC4 Error Count
FERR[6]
CERR[6]
14
14
6
0
6
0
Performance Monitoring Registers
CERR[5]
FERR[5]
13
13
5
0
5
0
Mindspeed Technologies™
FERR[4]
CERR[4]
Preliminary Information
12
12
4
0
4
0
FERR[11]
CERR[3]
FERR[3]
11
11
3
3
0
FERR[10]
FERR[2]
CERR[2]
10
10
2
2
0
FERR[1]
FERR[9]
CERR[1]
CERR[9]
1
9
1
9
Register Description
FERR[0]
FERR[8]
CERR[0]
CERR[8]
0
8
0
8
8
-
51