cx29503 Mindspeed Technologies, cx29503 Datasheet - Page 107

• Manufacturer Part Number: cx29503
• Description: Cx29503 Broadband Access Multiplexer Data Sheet
• Manufacturer: Mindspeed Technologies

CX29503 Data Sheet
4.2
Figure 4-2. DS1/E1 Framer Clock and Data Paths
29503-DSH-002-B
DS1/VC-11, and E1/VC-12
DS1/VT1.5, E1/VT2.0,
M13/E13
M13/E13
DEMUX
DEMUX
Tributary Mapper
MUX
MUX
DS1/E1 Clock and Data Options
fr1_txdat_m13
fr1_txclk_m13
fr1_dat_tx
m13_rxdat_fr1
DS1/VC-11, and E1/VC-12
m13_rxclk_fr1
DS1/VT1.5, E1/VT2.0,
The line side of each DS1/E1 framer interfaces to the M13 MUX/DEMUX and to the
SONET tributary mapper. The system side of each DS1/E1 framer interfaces to the
TSB. The MUXes that control clock and data paths to 28 of the DS1/E1 transmit and
receive framers are shown in
interfaces shown in
If the default value of a MUX is not desired, a clock must still be provided to the
default input to allow the MUX to be changed by a register that is in a downstream
block. In addition, the desired clock must be active before the MUX is switched to that
clock.
Tributary Mapper
smx_dat_rx
smx_clk_rx
Mindspeed Technologies™
fr1_clk_tx
RCVR_SEL
XMTR_SEL_n
0
1
Figure
Preliminary Information
2, 3
1
0
CLK_TXDS1 CLK_TXE1
4-2.
Figure
4-2. See
FLOOP
0
1
TSBCKI
Figure 2-2
RPOSI
RCKI
Transmitters
28xDS1/E1
fr1_rxclk_tsb
fr1_txclk_tsb
TPOSO
Clock Sources and Clock Configurations
for the top level view of the
28xDS1/E1
Receivers
RPCMO
TPCMI
TDLCKO
TFSYNC
RDLCKO,
RFSYNC
TSB
TSB
Rx
Tx
100702_033
4
-
3