cx29503 Mindspeed Technologies, cx29503 Datasheet - Page 333

• Manufacturer Part Number: cx29503
• Description: Cx29503 Broadband Access Multiplexer Data Sheet
• Manufacturer: Mindspeed Technologies

CX29503 Data Sheet
8.5.7
Table 8-57
Following the table are the register bit descriptions.
Table 8-57. Mapping Control/Status Registers
0x6380—Level 3 Mapping Control
Reset State
L3Map[1:0]
TUG3
SDHSSEn
29503-DSH-002-B
Offset (Hex)
6300–6307F
6381–6387
638–63FF
—
7
638D
6380
6388
6389
638A
638B
638C
638E
lists the Control and Status registers in the Tributary Mapping section of the memory map.
0x00
Level 3 Mapping control—Controls the data path interface to the SI-Bus interface. If the
TUG3 bit (bit 2) is set, then the selected mapping is TUG-3; otherwise, it is STS-1/AU-3.
The L3Map[1:0] (see
switches in the receive data path. For simplicity,
overhead data. See
TUG-3 mapping when set, otherwise STS-1/AU-3 mapping.
Discerns SS bits in AU-4/AU-3 SDH pointer interpretation and generation when set.
Mapping Control/Status Registers
—
6
GRPCFG1
GRPCFG2
GRPCFG3
GRPCFG4
GRPCFG5
GRPCFG6
GRPCFG7
Acronym
LVL3CFG
00 = unchannelized STS-1/AU-3 or TUG-3.
01 = tributary mapping via STS-1/AU-3 or TUG-3. This bit enables the tributary path.
10 = DS3 mapping via STS-1/AU-3 or TUG-3.
11 = E3 mapping via STS-1/AU-3 or TUG-3.
—
—
—
The specific tributary data path (PDH or clear channel) is controlled by the
ClearCh1, ClearCh2, ClearCh3, and ClearCh4 bits in the Group n Mapping
Control registers [addr: 0x6388 to 0x638E].
—
5
Figure 2-2
Mindspeed Technologies™
Figure
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
—
—
Preliminary Information
8-8) controls MUXes in the transmit data path and conceptual
for the top level view of the interfaces shown in
—
4
Clear on
Read
No
No
No
No
No
No
No
No
—
—
—
SDHSSEn
Undefined
Level 3 Mapping Control
Undefined
Group 1 Mapping Control
Group 2 Mapping Control
Group 3 Mapping Control
Group 4 Mapping Control
Group 5 Mapping Control
Group 6 Mapping Control
Group 7 Mapping Control
Undefined
3
Register Description
Figure 8-8
TUG3
2
does not show the data paths for
L3Map[1]
1
(Hex or Undefined)
Value After Reset
Figure
Register Description
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
—
—
—
L3Map[0]
8-8.
0
8
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