cx29503 Mindspeed Technologies, cx29503 Datasheet - Page 245

• Manufacturer Part Number: cx29503
• Description: Cx29503 Broadband Access Multiplexer Data Sheet
• Manufacturer: Mindspeed Technologies

CX29503 Data Sheet
0x5226—Feature3 Control Register
Default after reset:
Direction:
Modification:
PayldLp
RlineLp
TxFEACIE
FEACSin
RxFEACSNEIE
RxFEACIdleIE
29503-DSH-002-B
PayldLp
7
00(h)
Read/Write
Bit 4, static; bits 0–2 and 5–7, dynamic
Payload Loopback Enable—Set to enable a payload loopback from the receiver circuit through
the transmitter circuit back to the network. This loopback connects the received payload (after
decoding, frame recovery, and overhead extraction) to the transmitter input, where it is framed
and encoded again. The received data is still present on the receiver output signals.
A dynamic change of this bit can cause loss of data for a few clock cycles, until the channel is
internally synchronized. Activation/deactivation of a loopback causes internal circuits to
switch between clocks. After writing to this bit, the microprocessor should not access any of
the device registers (read or write) for the 20 slowest clock cycles.
Remote Line Loopback Enable—Set to enable loopback after decoding/encoding back to the
network. If the receiver FIFO is disabled (the RxFIFEn bit in the Feature5 register is clear) data
output of the B3ZS/HDB3 decoder connects to the transmitter encoder input. If the receiver
FIFO is enabled (RxFIFEn bit is set), data output of this FIFO connects to the transmitter
encoder input. LCVs are not preserved in this loopback. The received data is still presented to
all receiver blocks and is present on the receiver outputs.
A dynamic change of this bit can cause loss of data for a few clock cycles, until the channel is
internally synchronized. Activation/deactivation of a loopback causes internal circuits to
switch between clocks; after writing to this bit, the microprocessor should not access any of the
device registers (read or write) for the 20 slowest clock cycles.
Transmit FEAC Interrupt Enable—A control bit allows interrupts from the FEAC transmitter
when in DS3-C Bit Parity mode. When in single mode, the interrupt is asserted after every
transmission of the code word written in the Transmit FEAC Channel Byte register. When in
repetitive mode, the interrupt is asserted once the code word is transmitted 10 times. The
associated interrupt status is reported in TxFEACItr bit in the Transmit Data Link FEAC
Interrupt Status register [addr: 248].
FEAC Channel in Single Mode—DS3-C Bit Parity mode set to enable FEAC channel (in the
transmitter and the receiver) in a single mode, i.e., assert an interrupt after a single reception/
transmission of a code word. When clear, a repetitive mode is enabled, i.e., an interrupt is
asserted after completion of 10 repetitions of code word reception/transmission. In DS3-M13/
M23 and E3-G.751 modes, this bit has no effect.
Receive FEAC Stack Not Empty Interrupt Enable—A control bit that allows interrupts due to
detection of the FEAC stack being “not empty”, i.e., the Receive FEAC stack byte is holding
valid data. Active both in single and repetitive modes. The associated interrupt status is
reported in the RxFEACSNE bit in the Receive FEAC Interrupt Status register [addr: 251].
Receive FEAC Channel Idle Interrupt Enable—A control bit that allows interrupts due to
detection of the start of an idle pattern over an FEAC channel by the receiver circuit. Active
both in single and repetitive modes. The associated interrupt status is reported in the
RxFEACIdle bit in the Receive FEAC Interrupt Status register [addr: 251].
RlineLp
6
TxFEACIE
5
Mindspeed Technologies™
FEACSin
Preliminary Information
4
Rsvd
3
RxFEACSNEIE
2
RxFEACIdleIE
1
Register Description
RxFEACIE
0
8
-
115