cx29503 Mindspeed Technologies, cx29503 Datasheet - Page 114

• Manufacturer Part Number: cx29503
• Description: Cx29503 Broadband Access Multiplexer Data Sheet
• Manufacturer: Mindspeed Technologies

Clock Sources and Clock Configurations
Table 4-10. Payload TSB Clock Configurations
Table 4-11. Overhead TSB Clock Configurations
4.7
4-10
Payload Clock
(TSB_CLK) in TSB
Mode (TSBUS =
0×1
FOOTNOTE:
(1)
Overhead TSB Clock
(TSB_OCLK)
FOOTNOTE:
(1)
Description
TXE3_CLKSEL is located in the Clock Configuration register
TSBUS, CLEAR_DS3, and CLEAR_E3 are located in the TSB Module Operation
TXE3_CLKSEL is located in the Clock Configuration register
(1)
)
Description
Command and Status Processor (CSP) and
Microprocessor Clocks
Freq.MHz
44.736
44.736
44.736
44.736
51.84
The clocks for the CSP and Microprocessor Interface blocks are derived as shown in
Figure
operation. From the external point of view, the CSP operates in an asynchronous mode.
Freq. MHz
Serial DS3
Serial DS3
Interface
11.184
11.184
Serial E3
Serial E3
4-4. The CSP block utilizes line transmit clock sources for its internal
12.96
SI-Bus
Line
Mindspeed Technologies™
(unchannelized DS3)
(TSB Signal Type)
(28 × DS1, 21 × E1,
(unchannelized E3)
or mixed DS1/E1)
Preliminary Information
TSB Data Path
Row Number
(
Table 2-7
2, 3, and 4
Table 2-7
(16 × E1)
—
—
—
7
6
1
5
(Section
(Section
(1)
)
8.8).
8.8).
SIB_TXHSCLK / 4
Clock Source
SIB_TXHSCLK
CLK_TXDS3 / 4
CLK_TXDS3 / 4
CLK_TXDS3
CLK_TXDS3
CLK_TXDS3
CLK_TXDS3
Clock Source
(Section
8.8).
CK_SRC[1:0] pins = 0×0 or 0×1
CK_SRC[1:0] pins = 0×2
or 0×3
CLEAR_DS3 = 0×0
CK_SRC[1:0] pins = 0×2
or 0×3
CLEAR__E3 = 0×0
CK_SRC[1:0] pins = 0×2
or 0×3
CLEAR_DS3 = 0×1
CK_SRC[1:0] pins = 0×2
or 0×3
CLEAR_E3 = 0×1
CK_SRC[1:0] pins = 0×0
or 0×1
CK_SRC[1:0] pins = 0×2
or 0×3
TXE3_CLKSEL = 0×0
CK_SRC[1:0] pins = 0×2
or 0×3
TXE3_CLKSEL = 0×1
Configuration Bits
Configuration Bits
CX29503 Data Sheet
29503-DSH-002-B
(1)
(1)