cx29503 Mindspeed Technologies, cx29503 Datasheet - Page 184

• Manufacturer Part Number: cx29503
• Description: Cx29503 Broadband Access Multiplexer Data Sheet
• Manufacturer: Mindspeed Technologies

Register Description
8.3.2.7
Five receive Sa-Byte buffers [RSA4–RSA8] are double-buffered. All 5 registers are updated with the Sa bits
received in TS0 of odd frames at each receive multiframe interrupt [RMF; addr: 008]. Bit 0 of all RSA registers
contains data from Frame 1, Bit 1 contains data from Frame 3, Bit 2 contains data from Frame 5, etc. This gives
the processor a full 2 ms after RMF interrupt to read any Sa-Byte buffer before the buffer content changes. The
processor should ignore RSA buffer contents at all times during T1 mode and also when the receiver reports
loss-of-FAS alignment [FRED=1; addr: 049] in E1 mode.
0x5B—Receive Sa4 Byte Buffer (RSA4)
RSA4[7]
RSA4[6]
RSA4[5]
RSA4[4]
RSA4[3]
RSA4[2]
RSA4[1]
RSA4[0]
0x5C—Receive Sa5 Byte Buffer (RSA5)
RSA5[7]
RSA5[6]
RSA5[5]
RSA5[4]
RSA5[3]
RSA5[2]
RSA5[1]
RSA5[0]
8-54
RSA4[7]
RSA5[7]
7
7
Sa4 bit received in Frame 15
Sa4 bit received in Frame 13
Sa4 bit received in Frame 11
Sa4 bit received in Frame 9
Sa4 bit received in Frame 7
Sa4 bit received in Frame 5
Sa4 bit received in Frame 3
Sa4 bit received in Frame 1
Sa5 bit received in Frame 15
Sa5 bit received in Frame 13
Sa5 bit received in Frame 11
Sa5 bit received in Frame 9
Sa5 bit received in Frame 7
Sa5 bit received in Frame 5
Sa5 bit received in Frame 3
Sa5 bit received in Frame 1
RSA4[6]
RSA5[6]
6
6
Receive Sa-Byte Buffers
RSA4[5]
RSA5[5]
5
5
Mindspeed Technologies™
RSA4[4]
RSA5[4]
Preliminary Information
4
4
RSA4[3]
RSA5[3]
3
3
RSA4[2]
RSA5[2]
2
2
RSA4[1]
RSA5[1]
1
1
CX29503 Data Sheet
29503-DSH-002-B
RSA4[0]
RSA5[0]
0
0