cx29503 Mindspeed Technologies, cx29503 Datasheet - Page 212

• Manufacturer Part Number: cx29503
• Description: Cx29503 Broadband Access Multiplexer Data Sheet
• Manufacturer: Mindspeed Technologies

Register Description
0xAC—TDL 1 End Of Message Control (TDL1_EOM)
Unused bits are reserved and should be written to 0.
TDL1_EOM
0AD—Transmit Data Link FIFO 1 (TDL1)
TDL1[7:0]
8-82
TDL1[7]
—
7
7
End-of-Transmit Message. Writing any data value to TDL1_EOM marks the last byte of data
written into the transmit FIFO as the end of an HDLC message (FCS or Non-FCS mode) or
marks the end of a transmit circular buffer. The processor must write TDL1_EOM after
writing a complete message or the last byte of a circular buffer into TDL1 [addr: 0AD]. The
written data value is ignored and cannot be read back. Multiple HDLC messages are allowed to
be queued in the transmit FIFO simultaneously. In addition, the transition from one circular
buffer to another occurs only after the EOM byte of the current circular buffer has been sent.
Transmit Message Data—Output by the transmitter data link, from LSB to MSB, and sent on
the selected time slot bits. The processor writes 8-bit FIFO data during HDLC and Pack8
modes. During Pack6 mode, only the 6 LSBits TDL1[5:0] are used.
TDL1[6]
—
6
6
TDL1[5]
—
5
5
Mindspeed Technologies™
TDL1[4]
Preliminary Information
—
4
4
TDL1[3]
—
3
3
TDL1[2]
—
2
2
TDL1[1]
—
1
1
CX29503 Data Sheet
29503-DSH-002-B
TDL1[0]
—
0
0