cx29503 Mindspeed Technologies, cx29503 Datasheet - Page 202

• Manufacturer Part Number: cx29503
• Description: Cx29503 Broadband Access Multiplexer Data Sheet
• Manufacturer: Mindspeed Technologies

Register Description
8.3.2.11
Each framer contains one independent Data Link controller (DL1) which is programmed to send and receive
HDLC formatted or unformatted serial data over any combination of bits within a selected time slot. The serial
data channel operates at a multiple of 4 kbps up to the full 64 kbps time slot rate by selecting a combination of
time slot bits from odd, even, or all frames. DL1 contains a 64-byte receive and a 64-byte transmit buffer which
function either as programmable length circular buffers or full-length data FIFOs.
0xA4—DL1 Time Slot Enable (DL1_TS)
DL1_TS[7]
DL1_TS[6, 5]
DL1_TS[4:0]
8-72
DL1_TS[7]
7
DL1_TS[6]
Unchannelized—Test mode only, all time slots selected. Zero for normal operation.
Frame Select—Transmit and Receive Data Link 1 operates on data only during the specified
T1/E1 frames. Frame select options give the processor access to different types of data link
channels and overhead channels.
Time Slot Word Enable—Transmit and receive data link 1 operates on data only during the
specified time slot. During T1 mode, selecting time slot 0 enables data link operation on the F-
bit positions.
6
Data Link Registers
00 = all frames
01 = even frames only
10 = odd frames only
11 = not valid
Table 8-33. Data Link 1 Time Slot Selection
NOTE:
DL1_TS[5]
5
Mindspeed Technologies™
Overhead bit insertion is performed after TDL1, so internal transmitter overhead
insertion must be bypassed [TFRM; addr: 072] before processor-supplied overhead
can be output from TDL1.
DL1_TS[4:0]
DL1_TS[4]
00000
00001
11110
11111
Preliminary Information
—
.
.
.
4
DL1_TS[3]
3
F-bit (T1) or TS0 (E1)
TS1
TS30
TS31
DL1_TS[2]
2
Time Slot Enable
DL1_TS[1]
—
1
.
.
.
CX29503 Data Sheet
29503-DSH-002-B
DL1_TS[0]
0