tmp1940cyaf TOSHIBA Semiconductor CORPORATION, tmp1940cyaf Datasheet - Page 88

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tmp1940cyaf

Manufacturer Part Number
tmp1940cyaf
Description
32-bit Tx System Risc Tx19 Family
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet
7.4
Port 3 (P30–P37)
or CPU control/status pins. In either case, P30 and P31 are output-only pins.
and P3FC register bits are cleared, configuring P30 and P31 as output port pins and P32–P37 as input port
pins with pullup enabled. (Bits 0 and 1 in the P3CR and bit 3 in the P3FC are unused.) Upon reset, the
Output Latch (P3) is set to all 1s; so a logic 1 appears on P30 and P31.
address space is accessed. Likewise, when P31 is configured as WR (P3FC.P31F=1), the Write Strobe
signal is activated when external address space is accessed.
P36 are enabled, if they are configured as HWR (P3FC.P32F=1) and
Eight Port 3 pins can be individually programmed to function as either discrete general-purpose I/O pins
The P3CR and P3FC registers select the direction and function of the Port 3 pins. Upon reset, the P3CR
When P30 is configured as RD (P3FC.P30F=1), the Read Strobe signal is activated when external
P35 can be configured as BUSAK . While BUSAK is asserted, the internal pullup resistors for P32 and
TMP1940CYAF-46
R/
W
(P3FC.P36F=1) respectively.
TMP1940CYAF

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