tmp1940cyaf TOSHIBA Semiconductor CORPORATION, tmp1940cyaf Datasheet - Page 152

• Manufacturer Part Number: tmp1940cyaf
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

10.4.5
10.4.6
DMA Channel Priority
priority and channel 3 the lowest. For example, when transfer requests occur on channels 0 and 1
simultaneously, the channel 0 request is serviced first. The channel 1 request is left pending. So that the
channel 1 request is serviced, it must be maintained until data transfer completes on channel 0.
interrupts to be used as a DMA trigger instead of as an interrupt request. If such an interrupt is
programmed for edge sensitivity, the INTC internally maintains a transfer request. However, a level-
sensitive interrupt is not held in the INTC; thus the interrupt request signal must remain asserted until
the servicing of the DMA request begins.
channel 0 while a request on channel 1 is being serviced, the servicing of the channel 1 request is
suspended temporarily in order to service the channel 0 request first. After the channel 0 request has
been serviced, channel 1 resumes the remaining data transfer.
being serviced; that is, after all data in the DHR are written to a destination.
Interrupts
of a channel operation: either by normal channel termination or by abnormal termination of a bus cycle.
Note:
The DMAC provides a fixed priority for the four channels, with channel 0 always having the highest
Remember that the internally generated request is kept until the servicing of the request is finished.
External transfer requests come from the Interrupt Controller (INTC). The INTC can program any
A higher-priority channel always gets the attention of the DMAC. If a transfer request occurs on
Channel transitions take place at the boundary of a transfer size programmed for the current channel
The DMAC can generate an interrupt request (INTDMAn) to the TX19 core processor on completion
Normal Completion Interrupt
At this time, if the NIEn bit in the CCRn is set, an interrupt request is generated to the TX19 core
processor.
Abnormal Completion Interrupt
this time, if the AbIEn bit in the CCRn register is set, an interrupt request is generated to the TX19
core processor.
When a channel operation terminates by normal completion, the NC bit in the CSRn is set to 1.
When a channel operation terminates abnormally, the AbC bit in the CSRn register is set to 1. At
DMA channel priority exists only among those using the same type of bus request signal (SREQ
or GREQ).
TMP1940CYAF-110
TMP1940CYAF