tmp1940cyaf TOSHIBA Semiconductor CORPORATION, tmp1940cyaf Datasheet - Page 134

• Manufacturer Part Number: tmp1940cyaf
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

10.2.2
10.2.3
DMAC Block
Bus Snooping
the DMAC takes control of the processor data bus, the TX19 stops operating during snoop operations
until the DMAC relinquishes the bus to the processor. Snooping allows the DMAC to access the on-
chip RAM and ROM, and thus to use them as a DMA source or destination device.
of whether snooping is enabled or disabled, the DMAC assumes mastership of the TMP1940CYAF on-
chip bus (G-Bus) during DMA transfers. Therefore, as long as DMA transfers are in progress, the TX19
core processor can not access memory or I/O peripherals via the G-Bus; any attempt to do so causes the
processor pipeline to stall.
Note: If snooping is disabled, the TX19 core processor does not grant mastership of the processor data
The DMAC block diagram is shown in Figure 10.2.
The TX19 core processor supports snoop operations.
If snooping is enabled, the TX19 core processor grants the processor data bus to the DMAC. Because
The DMAC allows the enabling and disabling of the snooping function by software.
If snooping is disabled, the DMAC can not access the on-chip RAM and ROM. However, regardless
bus to the DMAC. Therefore, if the on-chip RAM or ROM is specified as a source or destination for
DMA transfers, a DMA acknowledge signal will never be returned, causing bus lockup.
Channel 3
Channel 2
Channel 1
31
Channel 0
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31
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B yt e C ount ƒ Œ ƒ W ƒ X ƒ ^
ƒ ` ƒ ƒ ƒ l ƒ ‹ ƒ R ƒ “ ƒ g ƒ
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ƒ X ƒ ^
Figure 10.2 DMAC Block Diagram
Source Address Register
Source Address Register (SARn)
Destination Address Register (DARn)
Byte Count Register (BCRn)
Channel Control Register (CCRn)
Channel Status Register (CSRn)
DMA Transfer Control Register (DTCRn)
DMA Control Register (DCR)
Data Holding Register (DHR)
TMP1940CYAF-92
[ ƒ ‹ ƒ Œ ƒ W
0
0
TMP1940CYAF