tmp1940cyaf TOSHIBA Semiconductor CORPORATION, tmp1940cyaf Datasheet - Page 277

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tmp1940cyaf

Manufacturer Part Number
tmp1940cyaf
Description
32-bit Tx System Risc Tx19 Family
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet
15.2.5
15.2.6
Conversion Time
conversion time of 10.75 s with 8-MHz fadc. The A/D conversion clock can be selected from fsys/2,
fsys/4 and fsys/8 through the programming of the ADCCK[1:0] field in the ADCCLK register. To
assure conversion accuracy, conversion time must be no shorter than 8.6 s.
Storing and Reading the A/D Conversion Result
ADREG37H/L). These registers are read-only.
ADREG37H/L sequentially. In other modes, channels AN0 and AN4 share the ADREG04H/L;
channels AN1 and AN5 share the ADREG15H/L; channels AN2 and AN6 share the ADREG26H/L;
and channels AN3 and AN7 share the ADREG37H/L.
registers.
The conversion process requires 86 conversion clocks per channel. For example, this results in a
Conversion results are loaded into conversion result high/low register pairs (ADREG04H/L to
In fixed-channel continuous conversion mode, conversion data goes into the ADREG04H/L to the
Table 15.4 shows the relationships between the analog input channels and the A/D conversion result
X = Don’t care
Fixed-Channel Single
Conversion Mode
Channel Scan Single
Conversion Mode
Fixed-Channel Continuous
Conversion Mode
Channel Scan Continuous
Conversion Mode
Table 15.2 Interrupt Request Generation in Each AD Conversion Mode
Mode
32 MHz
20 MHz
16 MHz
10 MHz
8 MHz
fsys
Table 15.3 Conversion Time
TMP1940CYAF-235
After a conversion
After a scan conversion
sequence
After each conversion
After every four conversions
After each scan conversion
sequence
Interrupt Request
Generation
Don’t use.
10.75 s
fsys/2
17.2 s
21.5 s
8.6 s
Conversion Clock
10.75 s
17.2 s
21.5 s
34.4 s
43.0 s
fsys/4
ITM0
X
X
0
1
X
TMP1940CYAF
ADMOD0
REPEAT
0
0
1
1
21.5 s
34.4 s
43.0 s
68.8 s
86.0 s
fsys/8
SCAN
0
1
0
1

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