tmp1940cyaf TOSHIBA Semiconductor CORPORATION, tmp1940cyaf Datasheet - Page 236

• Manufacturer Part Number: tmp1940cyaf
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Receive Data
Read Timing
Transmit Data
Write Timing
SCLK0 Output
TXD0
RXD0
INTTX0 Interrupt
INTRX0 Interrupt
Receive Data
Read Timing
Transmit Data
Write Timing
SCLK0 Output
TXD0
RXD0
INTTX0 Interrupt
INTRX0 Interrupt
(3) Full-Duplex Transmit/Receive Operations
operation, the double-buffering is enabled. When Receive Buffer 1 is filled with an 8-bit character,
it is transferred to Receive Buffer 2 (SC0BUF), and the receive-done interrupt (INTRX0) is
generated. While an 8-bit character is being received, an 8-bit character can be transmitted from
the TXD0 pin simultaneously. When a whole 8-bit character has been shifted out, the transmit-
done interrupt (INTTX0) is generated.
operation. The CPU must pick up the received character before the next character fills Receive
Buffer 1. Otherwise, the latter character is discarded. (The previous character is preserved.
Transmission proceeds with no error.)
by point A. No transimi/receive operation occurs until the transmit buffer is filled. In case the
transmit buffer is loaded after point A, the transmit/receive operation begins at that point, causing
the transimit/receive data to be corrupted. For system applications in which transmit underrun
conditions could occur, handshaking is required.
Restrictions on SCLK Configured as an Input
enough to support back-to-back transfers. When SCLK is configured as an output, one or more
wait cycles are automatically inserted to prolong the SCLK intervals. However, when SCLK is
Setting the SC0MOD1.FDPX0 bit enables full-duplex communication. In this mode of
In SCLK Output mode, loading the transimit buffer with a character restarts the transmit/receive
In SCLK Input Mode, the CPU must write a character to be transmitted into the transmit buffer
In I/O Interface mode, the CPU may be unable to access the receive or transmit buffer fast
Figure 13.33 Full-Duplex Transmit/Receive Operation in I/O Interface Mode
Figure 13.34 Full-Duplex Transmit/Receive Operation in I/O Interface Mode
A
bit 0
bit 0
bit 0
bit 0
TMP1940CYAF-194
bit 1
bit 1
bit 1
bit 1
(SCLK0 Output Mode)
(SCLK0 Input Mode)
bit 5
bit 5
bit 5
bit 5
bit 6
bit 6
bit 6
bit 6
bit 7
bit 7
bit 7
bit 7
TMP1940CYAF
A
bit 0
bit 0
bit 0
bit 0
bit 1
bit 1
bit 1
bit 1