tmp1940cyaf TOSHIBA Semiconductor CORPORATION, tmp1940cyaf Datasheet - Page 237

• Manufacturer Part Number: tmp1940cyaf
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

13.4.2
Mode 1 (7-Bit UART Mode)
operation, the parity bit can be added to the transmitted character, and the receiver can perform a parity
check on incoming data. Parity can be enabled and disabled through the programming of the PE bit in
the SC0CR. When PE = 1, the SCR0CR.EVEN bit selects even or odd parity.
Setting the SM[1:0] field in the SC0MOD0 to 01 puts the SIO0 in 7-bit UART mode. In this mode of
Example: Transmitting 7-bit UART characters with an even-parity bit
configured as an input, the SCLK input must be delayed by external hardware so that the CPU can
keep pace with the data rate. Generally, the wait period is a function of the fsys frequency and the
data rate. The following figure gives some indication of the relationsip between SCLK and fsys
frequencies for different wait periods. In reality, processing load during transfers also affect the
maximum SCLK frequency.
Settings in the main routine
P9CR
P9FC
SC0MOD
SC0CR
BR0CR
IMCCLH
SC0BUF
Transmit-done interrupt routine
INTCLR
Interrupt processing
End of interrupt processing
X = Don’t care,
Note:
Clocking conditions:
System clock:
High-speed clock gear: × 1 (fc)
Prescaler clock:
The above figure assumes that the DMAC is utilized for reads of the receive buffer and
writes of the transmit buffer.
start
– = No change
7
X
X
0
*
X
MHz
bit 0
2.0
1.5
1.0
0.5
0
6
0
1
0
*
X
0
5
1
1
1
*
1
1
TMP1940CYAF-195
Goes out first (transfer rate = 2400 bps @fc = 24.576 MHz)
4
X
X
0
1
*
1
High-speed (fc)
fperiph/4 (fperiph = fsys)
3
0
X
1
0
*
10
0
2
2
1
X
0
1
*
0
fsys
3
1
0
0
1
0
*
0
20
0
1
1
1
0
0
0
*
1
4
Sufficient wait period
30 32
5
Configures the P90 pin as TXD0.
Selects 7-bit UART mode.
Selects even parity.
Sets the transfer rate to 2400 bps.
Enables the INTTX0 interrupt and sets its priority
level to 4.
Loads the transmit buffer with a character.
Clears the interrupt request.
Wait period of one SCLK cycle
6
MHz
Wait period of one-half SCLK
cycle
No wait (free-running SCLK)
parity
even
TMP1940CYAF
stop