tmp1940cyaf TOSHIBA Semiconductor CORPORATION, tmp1940cyaf Datasheet - Page 256

• Manufacturer Part Number: tmp1940cyaf
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

INTS2 Interrupt
Request
PIN Bit
SDA
SCL
9
Example: When receiving N data words
Figure 14.16 Terminating Data Transmission in Master-Receiver Mode
so that a clock is generated on the SCL line once. With the ACK bit cleared, the master-receiver
holds the SDA line high, which signals the end of transfer to the slave-transmitter.
routine must generate a STOP condition to stop communication via the I
X = Don’t care
SBI0CR1
Reg.
End of interrupt
INTS2 interrupt (first to (N-2)th data reception)
Reg.
End of interrupt
INTS2 interrupt ((N-1)th data reception)
SBI0CR1
Reg.
End of interrupt
INTS2 interrupt (Nth data reception)
SBI0CR1
Reg.
End of interrupt
INTS2 interrupt (after completing data reception)
SBI0CR1
Reg.
End of interrupt
INTS2 interrupt (after data transmission)
Then, the SBI generates the INTS2 interrupt again, whereupon the INTS2 interrupt service
D7
Read out the received data after clearing the SBI0CR1.ACK bit.
1
D6
2
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
SBI0DBR
7 6 5 4 3 2 1 0
X X X X 0 X X X
X X X 0 0 X X X
0 0 1 0 0 X X X
7 6 5 4 3 2 1 0
0 0 1 0 0 X X X
SBI0DBR
SBI0DBR
SBI0DBR
SBI0DBR
D5
3
TMP1940CYAF-214
D4
4
D3
5
Set the number of bits to be received and specify whether
ACK is required.
Dummy read
Read the first to (N-2)th data words.
Disable generation of acknowledgement clock.
Read the (N-1)th data word.
Generate a clock once.
Read the Nth data word.
Generate a clock once.
Read the Nth data word.
D2
6
D1
7
D0
TMP1940CYAF
8
2
C bus.
Master to Slave
Slave to Master
Read out the received data
after setting the
SBI0CR1.BC[2:0] field to 001.
1
Negative acknowledge
(high) to transmitter