tmp1940cyaf TOSHIBA Semiconductor CORPORATION, tmp1940cyaf Datasheet - Page 254

• Manufacturer Part Number: tmp1940cyaf
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

14.6.3
SCL
SDA
PIN Bit
INTS2 Interrupt
Request
(2) Slave Mode
Transferring a Data Word
responsibility of the INTS2 interrupt service routine to test the MST bit in the SBI0CR to determine
whether the SBI is in master or slave mode.
(1) Master Mode (SBI0CR2.MST = 1)
Each time a data word has been transmitted or received, the INTS2 interrupt is generated. It is the
Master-Transmitter Mode (SBI0CR2.TRX = 1)
address via the I
direction bit transmitted by the master during the first eight SCL clock pulses. If the received slave
address matches its own address in the I2C0AR or is equal to the general-call address (00H), the
SBI pulls the SDA line low during the last (i.e., ninth) SCL clock for acknowledgement.
the PIN bit in the SBI0CR2 is cleared to 0. In slave mode, the SBI holds the SCL line low while
the PIN bit is 0.
whether the SBI is in master-transmitter or master-receiver mode.
further data to be sent from the master-transmitter. The master-transmitter must then generate a
STOP condition as described later to stop transmission.
bits per transfer is 8, then write the transmit data into the SBI0DBR. When using other data length,
program the BC[2:0] and ACK bits in the SBI0CR1, and then write the transmit data into the
SBI0DBR. When the SBI0DBR is loaded, the PIN bit in the SBI0SR is set to 1, and the transmit
data is shifted out from the SDA pin, clocked by the SCL clock. Once the transfer is complete, the
INTS2 interrupt is generated, the PIN bit is cleared, and the SCL line is pulled low. To transmit
further data, test the LRB bit again and repeat the above procedure.
Note:
Figure 14.13 Generation of a START Condition and a Slave Address
In slave mode, the following steps are required to receive a START condition and a slave
Upon detection of a START condition, the SBI clocks in a 7-bit slave address and a data
The INTS2 interrupt request is generated on the falling edge of the ninth SCL clock pulse, and
If the MST bit in the SBI0CR2 is set, then test the TRX bit in the same register to determine
Test the LRB bit in the SBI0SR. If the LRB bit is set, that means the slave-receiver requires no
If the LRB bit is cleared, that means the slave-receiver requires further data. If the number of
START Condition
The user can only use a DMA transfer:
- when there is only one master and only one slave on the I
- continuous transmission or reception is possible.
A6
2
1
C bus.
A5
2
TMP1940CYAF-212
A4
Slave Address + Direction Bit
3
A3
4
A2
5
A1
6
2
C bus; and
TMP1940CYAF
A0
7
R/
W
8
Acknowledgment
from slave
Master to Slave
Slave to Master
ACK
9