tmp1940cyaf TOSHIBA Semiconductor CORPORATION, tmp1940cyaf Datasheet - Page 121

• Manufacturer Part Number: tmp1940cyaf
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

8.3
8.3.1
8.3.2
Bus Arbitration
bus arbitration control signals, BUSRQ and BUSAK , are used to determine the bus master. One or more of
the external devices on the bus can have the capability of becoming bus master for the external bus, but not
the TMP1940CYAF internal bus.
The TMP1940CYAF provides support for an external bus master to take control of the external bus. Two
Bus Access Control
(G-Bus). Thus, external bus masters cannot access the TMP1940CYAF’s on-chip memory and
peripherals. The External Bus Interface (EBIF) logic in the TMP1940CYAF manages the arbitration of
the external bus; the CPU and on-chip DMAC do not participate in any way in this bus arbitration.
During external bus mastership, the CPU and the on-chip DMAC can access the internal memory
(RAM and ROM) and registers.
regain the bus until the external bus master releases the bus. If the CPU or the on-chip DMAC issues an
external memory access request, it is forced to wait until the TMP1940CYAF regains the bus.
Therefore, should BUSRQ be left asserted for a long time, the TMP1940CYAF might suffer system
lockups.
Bus Arbitration Flow
TMP1940CYAF samples BUSRQ at the end of each external bus cycle, as seen on its internal bus (G-
Bus). When the TMP1940CYAF has made an internal decision to grant the bus, it asserts BUSAK to
indicate to the requesting device that the bus is available. At the same time, the TMP1940CYAF puts
the address bus, the data bus and bus control signals in the high-impedance state.
(dynamic bus sizing). In that case, the TMP1940CYAF does not grant the bus until the entire transfer is
complete.
bus cycles to allow for sufficient read recovery time. In dummy cycles, the TMP1940CYAF has already
internally initiated a bus cycle on the G-Bus for the next external access. The TMP1940CYAF can only
accept an external bus request at the boundary of an internal G-Bus bus cycle. Therefore, if BUSRQ is
asserted during a dummy cycle, the TMP1940CYAF grants the bus after it completes the next external
bus cycle.
External bus masters can gain control of the external bus, but not the TMP1940CYAF internal bus
Once an external device assumes bus mastership, the CPU or the on-chip DMAC has no way to
External devices capable of becoming bus masters assert BUSRQ to request the bus. The
A load or store may require multiple bus cycles, depending on the port size of the addressed device
The TMP1940CYAF, if so programmed, automatically inserts dummy cycles between back-to-back
An external bus master must keep BUSRQ asserted until it is granted the bus.
A timing diagram of the bus arbitration sequence is shown in Figure 8.11.
TMP1940CYAF-79
TMP1940CYAF