tmp1940cyaf TOSHIBA Semiconductor CORPORATION, tmp1940cyaf Datasheet - Page 129

• Manufacturer Part Number: tmp1940cyaf
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

B01CS
(0xFFFF_E480)
9.2
Chip Select/Wait Control Registers
these registers consist of a chip select type field, a master enable bit, a data bus width bit, a wait state field
and a dummy cycle field.
and the BEXCS register defines the access characteristics for the rest of the address locations.
The organizations of the Chip Select/Wait Control registers are shown in Figure 9.4 to Figure 9.5. Each of
The B01CS register defines the CS0 and CS1 lines; the B23CS register defines the CS2 and CS3 lines;
Name
Read/Write
Reset Value
Function
Name
Read/Write
Reset Value
Function
Name
Read/Write
Reset Value
Function
Name
Read/Write
Reset Value
Function
Chip select output
Chip select output
waveform
00: ROM/RAM
Don’t use any other
value.
waveform
00: ROM/RAM
Don’t use any other
value.
Figure 9.4 Chip Select/Wait Control Registers
15
23
31
7
0
0
B0OM
B1OM
Chip Select/Wait Control Registers
W
W
14
22
30
6
0
0
TMP1940CYAF-87
13
21
29
5
Data bus
width
0: 16-bit
1: 8-bit
Data bus
width
0: 16-bit
1: 8-bit
B0BUS
B1BUS
12
20
28
4
0
0
Number of wait-state cycles
0000: No wait state, 0001: 1 wait state
0010: 2 wait states, 0011: 3 wait states
0100: 4 wait states, 0101: 5 wait states
0110: 6 wait states, 0111: 7 wait states
1111: (1 N) wait states, as determined by the
Don’t use any other value.
CS0
enable
0: Disable
1: Enable
Number of wait-state cycles
0000: No wait state, 0001: 1 wait state
0010: 2 wait states, 0011: 3 wait states
0100: 4 wait states, 0101: 5 wait states
0110: 6 wait states, 0111: 7 wait states
1111: (1 N) wait states, as determined by the
Don’t use any other value.
CS1
enable
0: Disable
1: Enable
B0E
B1E
11
19
27
W
W
3
0
0
0
0
WAIT pin
WAIT pin
TMP1940CYAF
10
26
18
W
W
2
1
1
B0W
B1W
Number of dummy
cycles (Read recovery
time)
00: 2 dummy cycles
01: 1 dummy cycle
10: No dummy cycle
11: Don’t use.
Number of dummy
cycles (Read recovery
time)
00: 2 dummy cycles
01: 1 dummy cycle
10: No dummy cycle
11: Don’t use.
17
25
1
9
0
0
0
0
B0RCV
B1RCV
W
W
24
16
0
8
1
0
1
0