tmp1940cyaf TOSHIBA Semiconductor CORPORATION, tmp1940cyaf Datasheet - Page 77

• Manufacturer Part Number: tmp1940cyaf
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

IMC0L
(0xFFFF_E000)
IMC0H
(0xFFFF_E002)
INTCLR
0xFFFF_E060)
6.5.2
6.5.3
Interrupt Mode Control Registers (IMCF–IMC0)
DMA triggering.
Interrupt Request Clear Register (INTCLR)
corresponding interrupt to be cleared.
Name
Read/Write
Reset Value
Function
Name
Read/Write
Reset Value
Function
Name
Read/Write
Reset Value
Function
Name
Read/Write
Reset Value
Function
Name
Read/Write
Reset Value
Function
These registers control the interrupt priority level, active polarity, either level or edge sensitivity, and
Loading the EICLR[5:0] field of this register with the IVRL[9:4] value of the IVR causes the
Note 1:
Note 2:
Note 3:
Note1:
Note2:
An interrupt request must not be cleared before the TX19 core processor reads the IVR value.
Follow the steps below to disable a particular interrupt with the Interrupt Controller (INTC).
1. Globally disable the acceptance of interrupts by the core processor by clearing the IEc bit of
2. Disable a desired interrupt with the INTC by clearing the ILx[2:0] field of the IMCxx register.
3. Execute the SYNC instruction.
4. Enable the acceptance of interrupts by the core processor by setting the IEc bit of the
Example:
Interrupt sensitivity must be programmed when interrupts are enabled.
For a complete list of the Interrupt Mode Control registers, see Chapter 19.
When an interrupt is used to trigger a DMAC channel, that DMAC channel must be put in
Ready state after the programming of the INTC.
the Status register.
Status register.
15
23
31
7
7
mtc0
sb
sync
mtc0
14
22
30
6
6
r0,
r0,
$sp, r31
TMP1940CYAF-35
r31
IMC**
Interrupt sensitivity
00: Low level
Must be set to 00.
Interrupt sensitivity
00: Low level
01: High level
10: Falling edge
11: Rising edge
EICLR5
EIM01
EIM11
EIM21
EIM31
13
21
Same as above
29
Same as above
5
5
0
0
0
0
(INT1)
(INT2)
; _DI ( ) ;
; IMC** = 0 ;
; _SYNC ( ) ;
; _EI ( ) ;
EICLR4
IVRL[9:4] value for an interrupt to be cleared
EIM00
EIM10
EIM20
EIM30
12
20
28
4
4
0
0
0
0
DMA
trigger
0: Disable
1: Enable
DMA
trigger
0: Disable
1: Enable
Same as
Same as
EICLR3
(INT1)
(INT2)
above
above
DM0
DM1
DM2
DM3
19
27
11
3
3
0
0
0
0
R/W
R/W
R/W
R/W
W
When DM0 = 0
When DM0 = 1
When DM0 = 1
When DM0 = 0
Interrupt Number 0 (Software Set)
DMAC channel select
Interrupt Number 1 (INT0 pin)
DMAC channel select
EICLR2
000: Interrupt disabled.
001–111: Priority level (1–7)
000–011: Channel number (0–3)
100–111: Don’t use.
000: Interrupt disabled.
001–111: Priority level (1–7)
000–011: Channel number (0–3)
100–111: Don’t use.
Interrupt Number 2 (INT1 pin)
Interrupt Number 3 (INT2 pin)
IL02
IL12
IL22
IL32
TMP1940CYAF
10
18
26
2
2
0
0
0
0
Same as above
Same as above
EICLR1
IL01
IL11
IL21
IL31
17
25
1
9
1
0
0
0
0
EICLR0
IL00
IL10
IL20
IL30
16
24
0
8
0
0
0
0
0