tmp1940cyaf TOSHIBA Semiconductor CORPORATION, tmp1940cyaf Datasheet - Page 151

• Manufacturer Part Number: tmp1940cyaf
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Normal Termination
Abnormal Termination
always occurs at the boundary of transfers programmed into the CCRn.TrSize field.
error.
Note:
A DMA channel terminates by normal completion in the following case. Normal completion
The paragraphs that follow summarize the cases in which a DMA channel terminates from an
Data transfers have terminated, with the BCRn decremented to 0.
Configuration errors
errors. A configuration error is reported before any data transfer takes place; therefore, in
case of a configuration error, the SARn, DARn and BCRn remain unaltered. When a DMA
channel has terminated from a configuration error, the AbC and Conf bits in the CSRn are
set. A configuration error occurs for the following cases:
Bus errors
bit in the CSRn is set.
A configuration error results when the channel initialization contains inconsistencies or
When a DMA channel has terminated from a bus error, the AbC bit and the BES or BED
The contents of the BCRn, SARn and DARn are not guaranteed when a channel has
terminated due to a bus error. Chapter 19 lists the reserved addresses that, if accessed,
cause a bus error.
Both the CCRn.SIO and CCRn.DIO bits are set.
The CCRn.Str bit is set when the NC or AbC bit in the CSRn is set.
The BCRn contains a value that is not an integer multiple of the transfer size
programmed into the CCRn.TrSiz field.
The SARn or DARn contains a value that is not an integer multiple of the transfer size
programmed into the CCRn.TrSiz field.
The CCRn.TrSiz and CCRn.DPS fields contain illegal combinations.
The CCRn.Str bit is set when the the BCRn contains a value of zero.
A bus error has been reported during a source read or destination write cycle.
TMP1940CYAF-109
TMP1940CYAF