tmp1940cyaf TOSHIBA Semiconductor CORPORATION, tmp1940cyaf Datasheet - Page 147

• Manufacturer Part Number: tmp1940cyaf
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

(6) Summary of Transfer Modes
(7) Address Change Options
settings.
CCRn respectively select address change directions for the Source Address Register (SARn) and
the Destination Address Register (DARn). While memory addresses can be programmed to
increment, decrement or remain constant, I/O addresses must be programmed to remain constant.
the source and destination addresses are incremented or decremented after each transfer. The bit
position can be bit 0, 4, 8, 12 or 16. Use of bit 0 is the regular increment/decrement mode in which
the address changes by 1, 2 or 4, according to the source or destination size. Two examples of how
other increment/decrement modes affect address changes are show below.
Transfer Request Edge/Level Address Mode
The DMAC can perform data transfers as follows according to the combination of mode
Address pointers can increment, decrement or remain constant. The SAC and DAC fields in the
The SACM and DACM fields in the DTCRn provide options to program bit positions at which
Example 1: When address bit 0 is selected in the SACM field and address bit 4 is selected in
Example 2: When address bit 8 is selected in the SACM field and address bit 0 is selected in
External
Internal
1st transfer
2nd transfer
3rd transfer
4th transfer
1st transfer
2nd transfer
3rd transfer
4th transfer
SAC: Programmed to increment the source address
DAC: Programmed to increment the destination address
TrSiz: Programmed to a transfer size of 32 bits
Source address: 0xA000_1000
Destination address: 0xB000_0000
SACM: 000
DACM: 001
SAC: Programmed to decrement the address
DAC: Programmed to decrement the address
TrSiz: Programmed to a transfer size of 16 bits
Source address: 0xA000_1000
Destination address: 0xB000_0000
SACM: 010
DACM: 000
the DACM field
the DACM field
0xA000_1000
0xA000_1004
0xA000_1008
0xA000_100C
0xA000_1000
0x9FFF_FF00
0x9FFF_FE00
0x9FFF_FD00
Low Level
Source
Source
Bit 0 is the source address bit at which address incrementation occurs.
Bit 8 is the source address bit at which address decrementation occurs.
Bit 4 is the destination address bit at which address incrementation occurs.
Bit 0 is the destination address bit at which address decrementation occurs.
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TMP1940CYAF-105
Dual
Dual
0xB000_0000
0xB000_0010
0xB000_0020
0xB000_0030
0xB000_0000
0xAFFF_FFFE
0xAFFF_FFFC
0xAFFF_FFFA
Destination
Destination
…
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Memory-to-memory
Memory-to-memory
Memory-to-I/O
I/O-to-memory
Data Flow
TMP1940CYAF