tmp1940cyaf TOSHIBA Semiconductor CORPORATION, tmp1940cyaf Datasheet - Page 5

• Manufacturer Part Number: tmp1940cyaf
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Handling Precaution
Part 1 TMP1940
TMP1940CYAF
1.
2.
3.
4.
5.
6.
7.
2.1
2.2
3.1
5.1
5.2
5.3
5.4
5.5
5.6
6.1
6.2
6.3
6.4
6.5
7.1
7.2
7.3
7.4
7.5
5.1.1
5.1.2
5.1.3
5.2.1
5.2.2
5.2.3
5.2.4
5.3.1
5.3.2
5.3.3
5.6.1
5.6.2
5.6.3
5.6.4
5.6.5
5.6.6
6.1.1
6.1.2
6.1.3
Features ................................................................................................................................................................... 1
Signal Descriptions ................................................................................................................................................. 5
Core Processor ........................................................................................................................................................ 9
Memory Map......................................................................................................................................................... 10
Clock/Standby Control .......................................................................................................................................... 11
Interrupts ............................................................................................................................................................... 29
I/O Ports ................................................................................................................................................................ 36
Pin Assignment .................................................................................................................................................. 5
Pin Usage Information ....................................................................................................................................... 6
Reset Operation ................................................................................................................................................. 9
Clock Generation............................................................................................................................................. 12
Clock Generator (CG) Registers...................................................................................................................... 14
System Clock Control Section ......................................................................................................................... 19
Prescalar Clock Control Section ...................................................................................................................... 21
Clock Frequency Multiplication Section (PLL)............................................................................................... 21
Standby Control Section .................................................................................................................................. 22
Overview ......................................................................................................................................................... 29
Interrupt Sources.............................................................................................................................................. 31
Interrupt Detection........................................................................................................................................... 33
Resolving Interrupt Priority ............................................................................................................................. 33
Register Description ........................................................................................................................................ 34
Port 0 (P00–P07) ............................................................................................................................................. 40
Port 1 (P10–P17) ............................................................................................................................................. 42
Port 2 (P20–P27) ............................................................................................................................................. 44
Port 3 (P30–P37) ............................................................................................................................................. 46
Port 4 (P40–P44) ............................................................................................................................................. 50
Main System Clock ................................................................................................................................. 12
Subsystem Clock..................................................................................................................................... 12
Clock Source Block Diagrams ................................................................................................................ 13
System Clock Control Registers.............................................................................................................. 14
ADC Conversion Clock .......................................................................................................................... 16
STOP/SLEEP Wake-up Interrupt Control Registers (INTCG Registers) ............................................... 16
Interrupt Request Clear Register ............................................................................................................. 18
Oscillation Stabilization Time When Switching Between NORMAL and SLOW Modes...................... 19
System Clock Output .............................................................................................................................. 20
Reducing the Oscillator Clock Drive Capability..................................................................................... 20
TMP1940CYAF Operation in NORMAL and Standby Modes............................................................... 23
CG Operation in NORMAL and Standby Modes ................................................................................... 23
Processor and Peripheral Block Operation in Standby Modes................................................................ 23
Wake-up Signaling .................................................................................................................................. 24
STOP Mode ............................................................................................................................................ 26
Returning from a Standby Mode............................................................................................................. 26
Interrupt Vector Register (IVR) .............................................................................................................. 34
Interrupt Mode Control Registers (IMCF–IMC0) .................................................................................. 35
Interrupt Request Clear Register (INTCLR) ........................................................................................... 35
Contents
i
TMP1940