tmp1940cyaf TOSHIBA Semiconductor CORPORATION, tmp1940cyaf Datasheet - Page 122

• Manufacturer Part Number: tmp1940cyaf
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

8.3.3
Internal clock
Internal address
External address
BUSRQ
BUSAK
Internal clock
Internal address
External address
BUSRQ
BUSAK
1. BUSRQ is sampled high.
2. The TMP1940CYAF recognizes the assertion of BUSRQ .
3. The TMP1940CYAF asserts BUSAK at the completion of the current bus cycle. The external bus
1. The external bus master has control of the bus.
2. When the external bus master no longer needs the bus, it deasserts BUSRQ .
3. In response to the deassertion of BUSRQ , the TMP1940CYAF deasserts BUSAK .
Relinquishing the bus
the bus to the TMP1940CYAF. Figure 8.12 shows the timing for an external bus master to relinquish
the bus.
master recognizes BUSAK and assumes bus mastership to start a bus transfer.
When the external bus master has completed its bus transactions, it deasserts BUSRQ to relinquish
TMP1940CYAF external access
TMP1940CYAF external access
Figure 8.12 External Bus Master Relinquishing the Bus
Figure 8.11 Bus Arbitration Timing Diagram
1
TMP1940CYAF
TMP1940CYAF
2
TMP1940CYAF-80
3
External bus master
External bus masters
TMP1940CYAF external access
TMP1940CYAF
1
‡ @‡ A ‡ B
external access
2 3
TMP1940CYAF
TMP1940CYAF
TMP1940CYAF