tmp1940cyaf TOSHIBA Semiconductor CORPORATION, tmp1940cyaf Datasheet - Page 275

• Manufacturer Part Number: tmp1940cyaf
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

15.2 Operation
15.2.1
15.2.2
15.2.3
Analog Reference Voltages
full-scale range for the internal resistor string, which divides the range into 1024 steps. The digital result
of the conversion is derived by comparing the sampled analog input voltage to the resistor string
voltages.
the VREFON bit is cleared, the internal reference voltage requires a recovery time of 3 s to stabilize
after the VREFON bit is again set to 1. This recovery time is independent of the system clock
frequency. The ADS bit in the ADMOD0 must then be set to initiate an conversion.
Selecting an Analog Input Channel (s)
the ADMOD0 affects the conversion channel(s) that will be selected as follows.
ADMOD1.ADCH[2:0] field defaults to 000. Thus, the AN0 pin is selected as the conversion channel.
The AN0–AN7 pins can be used as general-purpose input ports if not used as analog input channels.
Starting an A/D Conversion
set, or when a falling edge is applied to the ADTRG pin if the ADTRGE bit in the ADMOD1 is set.
When a conversion starts, the Busy flag (ADMOD0.ADBF) is set.
selected channel to begin a new conversion. The Conversion Result Store flag (ADREGxL.ADRxRF)
indicates whether the result register contains a valid digital result at that point.
is in progress.
The VREFH and VREFL pins provide the reference voltages for the ADC. These pins estabilish the
Clearing the VREFON bit in the ADMOD1 turns off the switch between VREFH and VREFL. Once
There are two basic conversion modes: fixed-channel mode and channel scan mode. The SCAN bit in
Refer to Table 15.1. After a reset, the ADMOD0.SCAN bit defaults to 0, and the
The ADC initiates a conversion or a sequence of conversions when the ADS bit in the ADMOD0 is
Writing a 1 to the ADS bit causes the ADC to abort any ongoing conversion and start sampling the
In external conversion trigger mode, a falling edge on the ADTRG pin is ignored while a conversion
Fixed-channel mode (ADMOD0.SCAN = 0)
channel selected from AN0–AN7 via the ADCH[2:0] field in the ADMOD1.
Channel scan mode (ADMOD0.SCAN = 1)
a specific group selected via the ADCH[2:0] field in the ADMOD1.
ADMOD1.ADCH[2:0]
When the SCAN bit in the ADMOD0 is cleared, the ADC runs conversions on a single input
When the SCAN bit in the ADMOD0 is set, the ADC runs conversions on sequential channels in
000
001
010
011
100
101
110
111
Table 15.1 Analog Input Channel Selection
TMP1940CYAF-233
Fixed-Channel Mode
ADMOD1.SCAN
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
0
AN0
AN0 AN1
AN0 AN1 AN2
AN0 AN1 AN2 AN3
AN4
AN4 AN5
AN4 AN5 AN6
AN4 AN5 AN6 AN7
Channel Scan Mode
ADMOD0.SCAN
TMP1940CYAF
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