tmp1940cyaf TOSHIBA Semiconductor CORPORATION, tmp1940cyaf Datasheet - Page 103

• Manufacturer Part Number: tmp1940cyaf
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

7.9
(1) P90 (TXD0) and P93 (TXD1)
Port 9 (P90–P97)
TXD0, TXD1
SIO channels. P90 and P93 are configurable as open-drain outputs.
P90 and P93 can be programmed to function as either general-purpose I/O pins or TXD output pins for
P90–P95
pins. Upon reset, P90–P95 are configured as input port pins, and the corresponding Output Latch (P9)
bits are set to 1.
reset clears the relevant P9CR and P9FC bits, configuring P90–P95 as input port pins.
P96–P97
open-drain outputs.
P96 and P97 to assume the high-impedance state.
connected between XT1 and XT2 to provide for Dual-Clock mode, which is controlled through System
Clock Control Registers 0 and 1 (SYSCR0 and SYSCR1).
P90–P95 can be individually programmed to function as discrete general-purpose or dedicated I/O
Setting the bits in the P9FC register configures the corresponding pin for SIO input or output pins. A
P96 and P97 function as general-purpose I/O pins. As output ports, P96 and P97 are configured as
Upon reset, the relevant Output Latch (P9) bits are set to 1, and the P9CR register bits are set, causing
P96 and P97 can also be used as the XT1 and XT2 pins; in this case, a low-frequency crystal is
Function Control
Direction Control
P9CR Write
P9FC Write
Output Latch
P9 Write
(bitwise)
(bitwise)
Reset
P9 Read
S
Figure 7.21 Port 9 (P90, P93)
TMP1940CYAF-61
A
B
Selector
Selector
S
S
B
A
open-drain outputs
Configurable as
ODE.ODE90
ODE.ODE93
TMP1940CYAF
P90 (TXD0)
P93 (TXD1)